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NCP4208 Datasheet(PDF) 18 Page - ON Semiconductor

Part # NCP4208
Description  Digital Programmable 8-Phase Synchronous Buck Converter
PDF  30 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP4208 Datasheet(HTML) 18 Page - ON Semiconductor

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3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the first data byte.
7. The slave asserts ACK on SDA.
8. The master sends the second data byte.
9. The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA and
the transaction ends.
The word write operation is shown in Figure 16.
Figure 16. Single Word Write to a Register
SLAVE
ADDRESS
COMMAND
CODE
DATA
(LSB)
A
A
W
SA
P
24
6
5
3
17
8
DATA
(MSB) A
10
9
Block Write
In this operation, the master device sends a command byte
and a byte count followed by the stated number of data bytes
to the slave device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the byte count N
7. The slave asserts ACK on SDA.
8. The master sends the first data byte
9. The slave asserts ACK on SDA.
10. The master sends the second data byte.
11. The slave asserts ACK on SDA.
12. The master sends the remainder of the data byes.
13. The slave asserts an ACK on SDA after each data
byte.
14. After the last data byte the master asserts a STOP
condition on SDA.
Figure 17. Block Write to a Register
SLAVE
ADDRESS
COMMAND
CODE
DATA
BYTE 1
A
A
W
S
24
6
5
3
17
8
9
BYTE COUNT
= N
AA
...
10
DATA
BYTE 2
A
... DATA
BYTE N
P
A
11
12
13
14
Read Operations
The NCP4208 uses the following I2C read protocols.
Read Byte
In this operation, the master device receives a single byte
from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on
SDA.
7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the Data Byte.
10. The master asserts NO ACK on SDA.
11. The master asserts a stop condition on SDA and
the transaction ends.
Figure 18. Single Byte Read from a Register
SLAVE
ADDRESS
COMMAND
CODE
DATA
A
A
W
SA
24
6
5
3
17
8
S
SLAVE
ADDRESS
A
R
10
9
11
P
Read Word
In this operation, the master device receives two data
bytes from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA.
7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the first Data Byte (low Data Byte).
10. The master asserts ACK on SDA.
11. The slave sends the second Data Byte (high Data
Byte).
12. The masters asserts a No ACK on SDA
13. The master asserts a stop condition on SDA and
the transaction ends.
Figure 19. Word Read from a Command Coder
SLAVE
ADDRESS
COMMAND
CODE
DATA
(LSB)
A
A
W
SA
24
6
5
3
17
8
S
SLAVE
ADDRESS
A
R
10
9
DATA
(MSB)
AP
12
11
13
In this operation, the master device sends a command
byte, the slave sends a byte count followed by the stated
number of data bytes to the master device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a REPEATED START condition
on SDA.



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