 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SAF7118H Datasheet(PDF) 8 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
SAF7118H Datasheet(HTML) 8 Page - NXP Semiconductors |
|
|
8 / 173 page  2004 Jul 22 8 Philips Semiconductors Product specification Multistandard video decoder with adaptive comb filter and component video input SAF7118 DNC13 39 N1 NC do not connect, reserved for future extensions and for testing DNC14 40 N2 I/pu do not connect, reserved for future extensions and for testing DNC18 41 P2 I/O do not connect, reserved for future extensions and for testing DNC15 42 N3 I/pd do not connect, reserved for future extensions and for testing EXMCLR 43 P3 I/pd external mode clear (with internal pull-down) CE 44 N4 I/pu chip enable or reset input (with internal pull-up) VDDD1 45 M4 P digital supply voltage 1 (peripheral cells) LLC 46 P4 O line-locked system clock output (27 MHz nominal) VSSD1 47 L4 P digital ground 1 (peripheral cells) LLC2 48 N5 O line-locked 1 ⁄ 2 clock output (13.5 MHz nominal) RES 49 P5 O reset output (active LOW) VDDD2 50 M5 P digital supply voltage 2 (core) VSSD2 51 L5 P digital ground 2 (core; substrate connection) CLKEXT 52 N6 I external clock input intended for analog-to-digital conversion of VSB signals (36 MHz) ADP8 53 P6 O MSB of direct analog-to-digital converted output data (VSB) ADP7 54 M6 O MSB − 1 of direct analog-to-digital converted output data (VSB) ADP6 55 L6 O MSB − 2 of direct analog-to-digital converted output data (VSB) ADP5 56 N7 O MSB − 3 of direct analog-to-digital converted output data (VSB) ADP4 57 P7 O MSB − 4 of direct analog-to-digital converted output data (VSB) ADP3 58 L7 O MSB − 5 of direct analog-to-digital converted output data (VSB) VDDD3 59 M8 P digital supply voltage 3 (peripheral cells) ADP2 60 M7 O MSB − 6 of direct analog-to-digital converted output data (VSB) ADP1 61 P8 O MSB − 7 of direct analog-to-digital converted output data (VSB) ADP0 62 N8 O LSB of direct analog-to-digital converted output data (VSB) VSSD3 63 L8 P digital ground 3 (peripheral cells) INT_A 64 P9 O/od I2C-bus interrupt flag (LOW if any enabled status bit has changed) VDDD4 65 M9 P digital supply voltage 4 (core) SCL 66 N9 I serial clock input (I2C-bus) VSSD4 67 L9 P digital ground 4 (core) SDA 68 P10 I/O/od serial data input/output (I2C-bus) RTS0 69 M10 O real-time status or sync information, controlled by subaddresses 11H and 12H RTS1 70 N10 O real-time status or sync information, controlled by subaddresses 11H and 12H RTCO 71 L10 O/st/pd real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see document “RTC Functional Description”, available on request); the RTCO pin is enabled via I2C-bus bit RTCE; see notes 5, 6 and Table 36 AMCLK 72 P11 O audio master clock output, up to 50% of crystal clock SYMBOL PIN TYPE(1) DESCRIPTION QFP160 HBGA156 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
