SAF7118H datasheet(39/173 Pages) PHILIPS

39 / 173 page

2004 Jul 22

Philips Semiconductors

Product speciﬁcation

Multistandard video decoder with adaptive

comb ﬁlter and component video input

SAF7118

8.2.2

DOWNFORMATTER

The block mainly consists of 2 parts: the colour difference

signal downsampler and the Y-path.

The colour difference signals are first passed through

low-pass filters which reduce alias effects due to the lower

data rate. The ITU sampling scheme requires that both

colour difference samples fit to the first Y sample of the

current time slot. Thus the CR signal is delayed by 1 clock

before it is fed to the multiplexer. The switch signal defines

the data multiplex phase at the output: a ‘0’ marks the first

clock of a time slot, this is a CB sample. The output is fed

through a register, so that the multiplexer runs with the

opposite phase.

The delay compensation for the Y signal already provides

most of the registers required for a small high-pass filter.

It can be used to compensate high frequency losses in the

analog part. It provides 2 dB gain at 6.75 MHz.

The Y high-pass filter frequency response is shown in

Fig.26. The DC gain of the filter is 1, so a limiter is required

at the filter output. The current implementation clips at the

maximum values of 0 and 511. The entire filter can be

controlled by the I2C-bus bit CMFI in subaddress 29H.

handbook, full pagewidth

MHB732

LOW-PASS

bypass

HIGH-PASS

CMFI

switch

(CR-CB)OUT

YOUT

delay compensation

Fig.24 Downformatter block diagram.

SAF7118H Datasheet(PDF) 39 Page - NXP Semiconductors