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DA7202 Datasheet(PDF) 11 Page - Dialog Semiconductor

Part # DA7202
Description  10 W Mono Class-D Amplifier for 2S Battery Devices
PDF  25 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

DA7202 Datasheet(HTML) 11 Page - Dialog Semiconductor

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DA7202
10 W Mono Class-D Amplifier for 2S Battery Devices
Company confidential
Datasheet
Revision 3a
20-Aug-2015
CFR0011-120-00 Rev 5
11 of 25
© 2015 Dialog Semiconductor
8.4
Gain
The DA7202 has a fixed gain of +18 dB.
Output volume is directly proportional to the input signal strength. It is assumed that any required
variation in output volume will be controlled by varying the DA7202 input signal. The input signal
amplitude can be reduced by the use of resistor dividers in conjunction with the known input
impedance.
8.5
Class D output stage
The class D output stage is connected directly to the PVDD (two cell battery pack) power supply.
High-efficiency operation is achieved by operating the output transistors as switches. The output
power transistors are either fully On or fully Off, providing a minimum resistance path for current from
the power supply to the load. The block’s outputs are connected directly to the speaker at OUT_P
and OUT_N.
Filterless operation is achieved by connecting a load (a speaker) between the output terminals of the
Class D ouput block. As a result, the voltage across the load represents a PWM (Pulse Width
Modulated) audio signal, while the output current in the load is a filtered, demodulated representation
of the input audio signal.
For filterless operation, the speaker load can be considered as a first order output filter with a cut-off
frequency well below the PWM carrier signal (the current in the load is a filtered version of the output
PWM voltage signal). See section 10.2 for further detail on speaker selection.
8.6
Power down (PDN_N)
The DA7202 is powered down by pulling the PDN_N pin low. When the device is powered down, a
controlled shutdown process is performed, thus ensuring that there are no audible artefacts (pops
and clicks) on the output path.
The time to disable the device is illustrated in Figure 16.
Table 7: Actions of the PDN_N pin
PDN_N Value
Description
0
Power Down
1
Active



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