DA7202

10 W Mono Class-D Amplifier for 2S Battery Devices

Company confidential

Datasheet

Revision 3a

20-Aug-2015

CFR0011-120-00 Rev 5

3 of 25

© 2015 Dialog Semiconductor

10.3 Recommended external component layout ........................................................................ 22

10.4 Recommended external components ................................................................................. 22

10.5 Capacitor selection.............................................................................................................. 22

10.5.1

Input and output capacitors ................................................................................. 22

10.5.2

Input and output capacitor properties .................................................................. 22

11 Package information ................................................................................................................... 24

11.1 Package outlines................................................................................................................. 24

11.2 Soldering information .......................................................................................................... 24

12 Ordering information .................................................................................................................. 24

Figures

Figure 1: DA7202 block diagram ........................................................................................................... 5

Figure 2: Connection diagram ............................................................................................................... 6

Figure 3: THD versus output power (8 Ω + 33 µH) ............................................................................. 12

Figure 4: THD versus output power (4 Ω + 33 µH) ............................................................................. 12

Figure 5: THD versus frequency (8 Ω + 33 µH) 4.5 V ......................................................................... 13

Figure 6: THD versus frequency (4 Ω + 33 µH) 4.5 V ......................................................................... 13

Figure 7: THD versus frequency (8 Ω + 33 µH) 8.2 V ......................................................................... 14

Figure 8: THD versus frequency (4 Ω + 33 µH) 8.2 V ......................................................................... 14

Figure 9: THD versus frequency (8 Ω + 33 µH) 9.0 V ......................................................................... 15

Figure 10: THD versus frequency (4 Ω + 33 µH) 9.0 V ....................................................................... 15

Figure 11: Maximum output power (Pout) versus supply voltage (8 Ω + 33 µH).................................. 16

Figure 12: Maximum output power (Pout) versus supply voltage (4 Ω + 33 µH).................................. 16

Figure 13: Efficiency versus output power (8 Ω + 33 µH) ................................................................... 17

Figure 14: Efficiency versus output power (4 Ω + 33 µH) ................................................................... 17

Figure 15: Start-up timing (260 µs from asserting PDN_N to valid output)......................................... 18

Figure 16: Shutdown timing (19 µs from de-asserting PDN_N to zero output)................................... 18

Figure 17: Power dissipation versus output power (8 Ω + 33 µH) ...................................................... 19

Figure 18: Power dissipation versus output power (4 Ω + 33 µH) ...................................................... 19

Figure 19: EMI performance with FCC Class-D limit also shown ....................................................... 20

Figure 20: Layout of recommended external components and their values ....................................... 22

Figure 21: Performance plot of the sample capacitor used in the example (below) ........................... 23

Figure 22: DA7202 package outline drawing (9-bump WL-CSP 0.5 mm pitch).................................. 24

Tables

Table 1: Pin description ......................................................................................................................... 6

Table 2: Absolute maximum ratings ...................................................................................................... 7

Table 3: Recommended operating conditions....................................................................................... 8

Table 4: Digital inputs (PDN_N) ............................................................................................................ 9

Table 5: Analog inputs (IN_P, IN_N) ..................................................................................................... 9

Table 6: Thermal protection................................................................................................................... 9

Table 7: Actions of the PDN_N pin...................................................................................................... 11

Table 8: Recommended external components ................................................................................... 22

Table 9: Ordering information.............................................................................................................. 24