DA14581 datasheet(39/152 Pages) DIALOG

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Datasheet

Revision 3.0

18-Dec-2015

CFR0011-120-00-FM Rev 5

39 of 152

DA14581

Low Power Bluetooth Smart SoC with optimized boot time

FINAL

R/W

UART_BC

Break Control Bit.

This is used to cause a break condition to be transmitted to

the receiving device. If set to one the serial output is forced

to the spacing (logic 0) state. When not in Loopback Mode,

as determined by MCR[4], the sout line is forced low until the

Break bit is cleared. If active (MCR[6] set to one) the

sir_out_n line is continuously pulsed. When in Loopback

Mode, the break condition is internally looped back to the

receiver and the sir_out_n line is forced low.

0x0

Reserved

0x0

R/W

UART_EPS

Even Parity Select.

This is used to select between even and odd parity, when

parity is enabled (PEN set to one). If set to one, an even

number of logic 1s is transmitted or checked. If set to zero,

an odd number of logic 1s is transmitted or checked.

0x0

R/W

UART_PEN

Parity Enable.

This bit is used to enable and disable parity generation and

detection in transmitted and received serial character

respectively.

0 = parity disabled

1 = parity enabled

0x0

R/W

UART_STOP

Number of stop bits.

This is used to select the number of stop bits per character

that the peripheral transmits and receives. If set to zero, one

stop bit is transmitted in the serial data.

If set to one and the data bits are set to 5 (LCR[1:0] set to

zero) one and a half stop bits is transmitted. Otherwise, two

stop bits are transmitted. Note that regardless of the number

of stop bits selected, the receiver checks only the first stop

bit.

0 = 1 stop bit

1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit

0x0

1:0

R/W

UART_DLS

Data Length Select.

This is used to select the number of data bits per character

that the peripheral transmits and receives. The number of bit

that may be selected areas follows:

00 = 5 bits

01 = 6 bits

10 = 7 bits

11 = 8 bits

0x0

Table 49: UART_LCR_REG (0x5000100C)

Bit

Mode

Symbol

Description

Reset

Table 50: UART_MCR_REG (0x50001010)

Bit

Mode

Symbol

Description

Reset

15:7

Reserved

0x0

R/W

UART_SIRE

SIR Mode Enable.

This is used to enable/disable the IrDA SIR Mode features

as described in "IrDA 1.0 SIR Protocol" on page 53.

0 = IrDA SIR Mode disabled

1 = IrDA SIR Mode enabled

0x0

R/W

UART_AFCE

Auto Flow Control Enable.

When FIFOs are enabled and the Auto Flow Control Enable

(AFCE) bit is set, hardware Auto Flow Control is enabled via

CTS and RTS.

0 = Auto Flow Control Mode disabled

1 = Auto Flow Control Mode enabled

0x0

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