ADV7181B datasheet(39/96 Pages) AD

39 / 96 page

ADV7181B

Rev. 0 | Page 39 of 96

VS and FIELD Configuration

The following controls allow the user to configure the behavior

of the VS and FIELD output pins, as well as the generation of

embedded AV codes:

•

ADV encoder-compatible signals via NEWAVMODE

•

PVS, PF

•

HVSTIM

•

VSBHO, VSBHE

•

VSEHO, VSEHE

•

For NTSC control:

NVBEGDELO, NVBEGDELE, NVBEGSIGN,

NVBEG[4:0]

NVENDDELO, NVENDDELE, NVENDSIGN,

NVEND[4:0]

NFTOGDELO, NFTOGDELE, NFTOGSIGN,

NFTOG[4:0]

•

For PAL control:

PVBEGDELO, PVBEGDELE, PVBEGSIGN,

PVBEG[4:0]

PVENDDELO, PVENDDELE, PVENDSIGN,

PVEND[4:0]

PFTOGDELO, PFTOGDELE, PFTOGSIGN,

PFTOG[4:0]

NEWAVMODE New AV Mode, Address 0x31 [4]

When NEWAVMODE is 0, EAV/SAV codes are generated to

suit ADI encoders. No adjustments are possible.

Setting NEWAVMODE to 1 (default) enables the manual

position of the VSYNC, Field, and AV codes using Registers

0x34 to 0x37 and 0xE5 to 0xEA. Default register settings are

CCIR656 compliant; see Figure 20 for NTSC and Figure 25 for

PAL. For recommended manual user settings, see Table 54 and

Figure 21 for NTSC; see Table 55 and Figure 26 for PAL.

HVSTIM Horizontal VS Timing, Address 0x31 [3]

The HVSTIM bit allows the user to select where the VS signal is

asserted within a line of video. Some interface circuitry may

require VS to go low while HS is low.

When HVSTIM is 0 (default), the start of the line is relative to

HSE.

When HVSTIM is 1, the start of the line is relative to HSB.

VSBHO VS Begin Horizontal Position Odd, Address 0x32 [7]

The VSBHO and VSBHE bits select the position within a line at

which the VS pin (not the bit in the AV code) becomes active.

Some follow-on chips require the VS pin to only change state

when HS is high/low.

When VSBHO is 0 (default), the VS pin goes high at the middle

of a line of video (odd field).

When VSBHO is 1, the VS pin changes state at the start of a line

(odd field).

VSBHE VS Begin Horizontal Position Even, Address 0x32 [6]

The VSBHO and VSBHE bits select the position within a line at

which the VS pin (not the bit in the AV code) becomes active.

Some follow-on chips require the VS pin to only change state

when HS is high/low.

When VSBHE is 0 (default), the VS pin goes high at the middle

of a line of video (even field).

When VSBHE is 1, the VS pin changes state at the start of a line

(even field).

VSEHO VS End Horizontal Position Odd, Address 0x33 [7]

The VSEHO and VSEHE bits select the position within a line at

which the VS pin (not the bit in the AV code) becomes active.

Some follow-on chips require the VS pin to only change state

when HS is high/low.

When VSEHO is 0 (default), the VS pin goes low (inactive) at

the middle of a line of video (odd field).

When VSEHO is 1, the VS pin changes state at the start of a line

(odd field).

VSEHE VS End Horizontal Position Even, Address 0x33 [6]

The VSEHO and VSEHE bits select the position within a line at

which the VS pin (not the bit in the AV code) becomes active.

Some follow-on chips require the VS pin to only change state

when HS is high/low.

When VSEHE is 0 (default), the VS pin goes low (inactive) at

the middle of a line of video (even field).

When VSEHE is 1, the VS pin changes state at the start of a line

(even field).

PVS Polarity VS, Address 0x37 [5]

The polarity of the VS pin can be inverted using the PVS bit.

When PVS is 0 (default), VS is active high.

When PVS is 1, VS is active low.

ADV7181B Datasheet(PDF) 39 Page - Analog Devices

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