AMIC110 datasheet(95/214 Pages) TI1

95 / 214 page

MPU

PLL

PER

PLL

DDR

PLL

CORE

PLL

LCD

PLL

VDDS_PLL_MPU

VDDS_PLL_CORE_LCD

VDDA1P8V_USB0

VDDS_PLL_DDR

AMIC110

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SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016

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Power and Clocking

6.1.4

Digital Phase-Locked Loop Power Supply Requirements

NOTE

The LCD module is not supported for this family of devices, but the "LCD" name is still

present in some supply voltage or PLL names.

The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor

of the AMIC110 device. The AMIC110 device integrates five different DPLLs—Core DPLL, Per DPLL, LCD

DPLL, DDR DPLL, MPU DPLL.

Figure 6-8 shows the power supply connectivity implemented in the AMIC110 device. Table 6-1 provides

the power supply requirements for the DPLL.

Figure 6-8. DPLL Power Supply Connectivity

Table 6-1. DPLL Power Supply Requirements

SUPPLY NAME

DESCRIPTION

MIN NOM

MAX

UNIT

VDDA1P8V_USB0

Supply voltage range for USBPHY and PER DPLL, Analog, 1.8 V

1.71

1.8

1.89

Max peak-to-peak supply noise

mV (p-p)

VDDS_PLL_MPU

Supply voltage range for DPLL MPU, analog

1.71

1.8

1.89

Max peak-to-peak supply noise

mV (p-p)

VDDS_PLL_CORE_LCD

Supply voltage range for DPLL CORE and LCD, analog

1.71

1.8

1.89

Max peak-to-peak supply noise

mV (p-p)

VDDS_PLL_DDR

Supply voltage range for DPLL DDR, analog

1.71

1.8

1.89

Max peak-to-peak supply noise

mV (p-p)

AMIC110 Datasheet(PDF) 95 Page - Texas Instruments

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