DP7172 datasheet(9/11 Pages) COPAL

9 / 11 page

DP7172

For RAB = 100 k and the B terminal open circuited, the

following output resistance RWA will be set for the indicated

Wiper register codes.

Table 8. CODES AND CORRESPONDING RWA

RESISTANCE FOR RAB = 100 k ,VDD =5V

D (Dec.)

RWA ( )

Output State

255

441

Full Scale

128

50,050

Midscale

99,659

1 LSB

100,050

Zero Scale

Typical device to device resistance matching is lot

dependent and may vary by up to 20%.

SPI Compatible 3 Wire Serial Bus

Control of DP7172 is through a

SPI compatible

digital interface (SDI, CS, and CLK).

The CLK input is rising edge sensitive and requires crisp

transitions to avoid clocking incorrect data into the serial

input register. When CS is low, the clock loads data into the

serial register on each positive clock edge (Figure 1). Each

8 bit serial word must be loaded starting with the MSB. The

format of the word is shown in Table 6.

Data loaded into

serial input register is

transferred to the internal Wiper register when the CS line

returns to logic high. Extra MSB bits are ignored.

ESD Protection

GND

LOGIC

Digital

Input

GND

Potentiometer

Figure 15. ESD Protection Networks

Terminal Voltage Operating Range

The DP7172 VDD and GND power supply define the

limits for proper 3 terminal digital potentiometer operation.

Signals or potentials applied to terminals A, B or the wiper

must remain inside the span of VDD and GND. Signals

which attempt to go outside these boundaries will be

clamped by the internal forward biased diodes.

W, A, B

DP7172

LOGIC

GND

Figure 16.

VDD

Power up Sequence

Because ESD protection diodes limit the voltage

compliance at terminals A, B, and W (see Figure 15), it is

recommended that VDD/GND be powered before applying

any voltage to terminals A, B, and W. The ideal power up

sequence is: GND, VDD, digital inputs, and then VA/B/W. The

order of powering VA, VB,VW, and the digital inputs is not

important as long as they are powered after VDD/GND.

Power Supply Bypassing

Good design practice employs compact, minimum lead

length layout design. Leads should be as direct as possible.

It is also recommended to bypass the power supplies with

quality low ESR Ceramic chip capacitors of 0.01

Fto

0.1 F. Low ESR 1 Fto10 F tantalum or electrolytic

capacitors can also be applied at the supplies to suppress

transient disturbances and low frequency ripple. As a further

precaution digital ground should be joined remotely to the

analog ground at one point to minimize the ground bounce.

DP7172

GND

10 F

0.1 F

Figure 17. Power Supply Bypassing

VDD

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