ASX340AT datasheet(51/54 Pages) ONSEMI

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ASX340AT

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TABLE 50. TWO-WIRE SERIAL BUS CHARACTERISTICS

(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;

VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; TA = 25°C)

Parameter

Units

Fast Mode

Standard Mode

Symbol

Parameter

Units

Max

Min

Max

Min

Symbol

After this period, the first clock

pulse is generated

tHD;STA

4.0

−

0.6

−

LOW period of the SCLK clock

tLOW

4.7

−

1.3

−

HIGH period of the SCLK clock

tHIGH

4.0

−

0.6

−

Se-up time for a repeated START

condition

tSU;STA

4.7

−

0.6

−

Data hold time

tHD;DAT

3.455

0.95

Data set-up time

tSU;DAT

250

−

1006

−

Rise time of both SDATA and SCLK

signals

−

1000

20 + 0.1Cb7

300

Fall time of both SDATA and SCLK

signals

−

300

20 + 0.1Cb7

300

Set-up time for STOP condition

tSU;STO

4.0

−

0.6

−

Bus free time between a STOP

and START condition

tBUF

4.7

−

1.3

−

Capacitive load for each bus line

−

400

−

400

Serial interface input pin

capacitance

CIN_SI

−

3.3

−

3.3

SDATA max load capacitance

CLOAD_SD

−

SDATA pull-up resistor

RSD

1.5

4.7

1.5

4.7

1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

2. Two-wire control is I2C-compatible.

3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.

6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This

will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period

of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode

I2C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

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