ASX340AT datasheet(10/54 Pages) ONSEMI

10 / 54 page

ASX340AT

www.onsemi.com

SOC DESCRIPTION

Detailed Architecture Overview

Sensor Core

The sensor consists of a pixel array, an analog readout

chain, a 10-bit ADC with programmable gain and black

offset, and timing and control as illustrated in Figure 4.

Communication

10−Bit Data

to IFP

Clock

Control Register

Analog Processing

Array

Timing and Control

ADC

Figure 4. Sensor Core Block Diagram

Pixel Array Structure:

The sensor core pixel array is configured as 728 columns

by 560 rows, as shown in Figure 5.

Figure 5. Pixel Array Description

demosaic rows

Active pixel array

640 x 480

(not to scale)

Pixel logical address = (727, 559)

Pixel logical address = (0, 0)

lens alignment rows

(0, 0)

(40, 36)

(687, 523)

Black rows used internally for automatic black level

adjustment are not addressed by default, but can be read out

in raw output mode via a register setting.

There are 728 columns by 560 rows of optically-active

pixels (that is, clear pixels) that include a pixel boundary

around the VGA (640 x 480) image to avoid boundary

effects during color interpolation and correction. Among the

728 columns by 560 rows of clear pixels, there are 36 lens

alignment rows on the top and bottom, and 40 lens alignment

columns on the left and right; and there are 4 demosaic rows

and 4 demosaic columns on each side.

Figure 6 illustrates the process of capturing the image.

The original scene is flipped and mirrored by the sensor

optics. Sensor readout starts at the lower right corner. The

image is presented in true orientation by the output display.

ASX340AT Datasheet(PDF) 10 Page - ON Semiconductor

ASX340AT Datasheet(HTML) 10 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL