AX2061 datasheet(11/18 Pages) ONSEMI

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AX2061

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Figure 3. Serial Interface Timing

SPI Timing

MOSI

MISO

T10

T11

T12

T13

R10

R11

R12

R13

Tssd

Tssz

Tcl Tch Tck

Tst

SEL

CIRCUIT DESCRIPTION

This section describes the bits of the register bank in

detail.

No checks are made whether the programmed

combination of bits makes sense! Bit 0 is always the LSB.

NOTE: Whole registers or register bits marked as

reserved should be kept at their default values.

NOTE: All addresses not documented here must not be

accessed, neither in reading nor in writing.

SPI Frame Formats

SPI transactions start with a falling edge on SEL. The first

four bits indicate the command, the following bits are

interpreted according to the command bits.

SPI transaction can be of variable length. The first 4 bits

of each SPI transaction code the command to be executed by

the AX2061. The first command bit, T0, distinguishes

Write (0) from Read(1) accesses. The following three

command bits (T1:T3) specify the register to access.

Even though many registers can be read as well as written,

reading a register is never required for the functionality of

the AX2061.

consecutive data elements as required can be read or written

in a single SPI transaction. All other registers are twelve bits

long.

Table 13. REGISTER OVERVIEW

Cmd

Name

Reset

Bit

Description

T1 :T2

:T3

000

PIXELDA

−−−−−

PIXELDATA…

Pixel Data

010

CONFIG

0000

0001

0000

RST

−

ENA

DIV

CLK

SRC

FRM

CLK

SRC

FRM

SYNC

LATCH[1:0]

MODE[3:0]

Configuration

011

DIVIDER

0000

PRESCALER[3:0]

DIVIDER[7:0]

Divider

100

CONTRA

0000

0010

0111

REVISION[7:0]

CONTRAST[3:0]

Contrast

101

PINCFG

0111

LAT

CHR

LATCHDRV[2:0]

SYS

CLKR

SYSCLKDRV[2:0]

ICLKR

ICLKDRV[2:0]

Configuration

110

INT

0101

0000

0001

reserved

CONTRAST_O

FF[1 :0]

reserved

BUF_CUR[3:0]

Internal

Configuration

111

OSCILLA

TOR

0000

0010

0011

reserved

CONF

EN_OSC_

PROG

FREQ_OSC[3:0]

reserved

Oscillator

frequency

programming

Pixel Data Register

The first command bit, T0, distinguishes Write (0) from

Read(1) accesses. The command code (T1:T2:T3 = 000) is

followed by a 10 bit Pixel Address (PA), and two dummy

bits. After that, Pixel Data (PD) can be read or written, one

pixel at a time. The Pixel Address auto increments. An

arbitrary number of consecutive pixels may be read or

written in a single transaction.

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