AX2061

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13

PINCFG Register

Table 20. PINCFG REGISTER

Name

Bits

R/W

Reset

Description

ICLKDRV

2:0

RW

111

ICLK drive mode

ICLKR

3

R

−

ICLK pad observation

SYSCLKDRV

6:4

RW

111

SYSCLK drive mode

SYSCLKR

7

R

−

SYSCLK pad observation

LATCHDRV

10:8

RW

111

LATCH drive mode

LATCHR

11

R

−

LATCH pad observation

Table 21. ICLK DRIVE MODE

Bits

Meaning

000

Drive 0

001

Drive 1

010

Internal 32 kHz oscillator clock

011

Divider output clock

100

Frame sync output

101

Latch output

111

High Impedance / Input

Table 22. SYSCLK DRIVE MODE

Bits

Meaning

000

Drive 0

001

Drive 1

010

Internal 32 kHz oscillator clock

011

Divider output clock

100

Frame sync output

101

Latch output

111

High Impedance / Input

Table 23. LATCH DRIVE MODE

Bits

Meaning

000

Drive 0

001

Drive 1

010

Internal 32 kHz oscillator clock

011

Divider output clock

100

Frame sync output

101

Latch output

111

High Impedance / Input

INT Register

Table 24. INT REGISTER

Name

Bits

R/W

Reset

Description

CONTRAST_OFF[1:0]

9:8

RW

01

Contrast offset adjustment, for Contrast bits see CONTRAST Register

BUF_CUR

3:0

RW

0001

Internal setting of the LCD Drive Voltage Buffers. MUST BE SET TO 1111.

Table 25. CONTRAST OFFSET CODING

Bits

Meaning

00

2 LSB, 40 mV offset

01

Default

10

1 LSB, 20 mV offset

11

−1 LSB, −20 mV offset