ACE93C46A/56A/66A

Three-wire Serial EEPROM

VER 1.3

4

Pin Descriptions

(A)

SERIAL CLOCK (SCL)

The rising edge of this SCL input is to latch data into the EEPROM device while the rising edge of

this clock is to clock data out of the EEPROM device.

(B)

CHIP SELECT (CS)

This is the chip select input signal for the serial EEPROM device.

.

(C)

SERIAL DATA INPUT (DI)

This is data input signal for the serial device.

(D)

SERIAL DATA OUTPUT (DO)

This is data output signal for the serial device.

(E)

INTERNAL

ORGANIZATION (ORG)

This is internal organization input signal for the serial EEPROM device. When the ORG pin is

connected to VCC or unconnected the EEPROM is organized as 64/128/256 word of 16 bits each

and when ORG pin is connected to ground the EEPROM is organized as 128/256/512 byte of 8

bits each. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they

are internally recognized as VIH.

Memory Organization

The ACE93C46A/56A/66A memory is organized either as bytes (x8) or as words (x16). If Internal

Organization (ORG) is unconnected (or connected to VCC) the words (x16) organization is selected;

When Internal Organization is connected to ground the bytes (x8) organization is selected.

Instruction set

Instruction

Device

Type

SB

Op

code

Address

Data

Comments

*8

(1) (2)

*16

(1) (3)

*8

*16

READ

ACE93C46A

ACE93C56A

ACE93C66A

1

1

1

10

10

10

Reads date stored

in memory, at

specified address.

EW EN

ACE93C46A

ACE93C56A

ACE93C66A

1

1

1

00

00

00

11XXXXX

11XXXXXXX

11XXXXXXX

11XXXX

11XXXXXX

11XXXXXX

W rite enable

must precede all

programming

modes.

EW DS

ACE93C46A

ACE93C56A

ACE93C66A

1

1

1

11

11

11

00XXXXX

00XXXXXXX

00XXXXXXX

00XXXX

00XXXXXX

00XXXXXX

Disables all

programming

instructions.

ERASE

ACE93C46A

1

01

Erase memory