OUT

IN

SW

ON(min)

V

V

f

t

=

´

IN

ON(min)

SW

PEAK

ISENSE

OUT

V

t

f

I

L

R

C

´

´

=

+

DELAY

COMP

0.7 V

t

C

28

A

=

´

m

TPS92513, TPS92513HV

www.ti.com

SLVSCX6 – APRIL 2015

8.4 Device Functional Modes

8.4.1 Start-Up

To reduce inrush current and to keep the regulator in control during all startup conditions the TPS92513 employs

a startup mode that behaves differently than during normal operation (regulation mode). The UVLO conditions

must be satisfied before the TPS92513 is allowed to switch. When the UVLO pin is held low the device enters a

low-power shutdown mode, and some internal circuits are deactivated to conserve power. When UVLO returns

high these circuits are enabled, which results in a delay of approximately 50 µs (typical) before switching starts.

During start-up the TPS92513 operates in a minimum pulse width mode which is an open-loop control. At the

start of each switching cycle the internal oscillator initiates a SET pulse. The high-side MOSFET turns on with a

minimum pulse width of 140 ns (typical), independent of the COMP voltage. The device does not pulse skip.

While operating in minimum pulse width mode, the LED bypass capacitor is being charged causing an in-rush

current. Also, the COMP voltage begins to rise as the error amplifier output current charges the compensation

capacitor. When the COMP voltage reaches approximately 0.7 V, the error amplifier is ensured to be out of

saturation and to have sufficient gain to regulate the loop. The TPS92513 then transitions from minimum pulse

width mode to regulation mode. During regulation mode the error amplifier is now in closed-loop control of the

system. The gain of the error amplifier quickly increases the duty cycle, which causes the output voltage to

increase. Once the output voltage approaches the forward voltage of the LED string, the LED current quickly

begins to increase until it reaches regulation.

There is a slight delay from the time the VIN and EN UVLO conditions are satisfied until the time the error

amplifier has control of the feedback loop. This delay is a result of the time it takes COMP to charge the

compensation capacitor to 0.7 V. This delay can be approximated as shown in Equation 10.

(10)

(11)

8.4.2 Minimum Pulse Width and Limitations

The TPS92513 is designed to output a minimum pulse width during each switching cycle of 140 ns (typical). The

control loop cannot regulate the system to an on-time less than this amount, and it does not skip pulses. When

attempting to operate below the minimum on-time the system loses regulation and the LED current increases.

This puts a practical limitation on the system operating conditions, as shown in Equation 12.

(12)

The system can avoid this operating condition by limiting the maximum input voltage as shown in Equation 12. If

the input voltage cannot be limited due to application, then the switching frequency can be lowered, or the output

voltage increased. This region of operation typically occurs with high input voltages, high operating frequencies,

and low output voltages.

8.4.3 Maximum Duty Cycle and Bootstrap Voltage (BOOT)

The TPS92513 requires a small 0.1 µF ceramic capacitor between the BOOT and PH pins to provide the gate

drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET turns

off, and the freewheeling rectifier diode conducts. A ceramic capacitor with an X7R or X5R dielectric and a

minimum voltage rating of 10 V is recommended.

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