Global Video Control Register (I

Register Name (address): GLOBALCTRL (0x0819h)

7

654321

0

D_ID5

D_ID4

D_ID3

D_ID2

D_ID1

D_ID0

PS

BV

Bit 0

Blank Video. When this bit is a one, blank the video output. When this bit is a zero allow normal video out. This register

bit is OR’d with the other video blank signals, both active and static, and sent to the preamplifier as BLANK_OUT.

Bit 1

Power Save. When this bit is a one, shut down the analog circuits to support sleep mode. When this bit is a zero

(default) enable the analog circuits for normal operation. This register bit is fed to the preamplifier interface as

PWR_SAVE so that the amplifier can be put in to low power sleep mode. It is also OR’d with the blanking signals to

blank the video.

Bits 7–2 Die ID. These bits are read only masked so that they can be assigned a value to differentiate between masked dies and

die revisions.

PLL Range Register (I

Register Name (address): CLMP/PLL/VBL/OOR (0x081Eh)

7

654321

0

INT

BIS

CLMP

FRE

OOR

VBL

PFR1

PFR0

Bits 1–0 PLL Frequency Range Control. These bits assist the PLL in locking to the desired pixel frequency. They are set based

upon the nominal desired horizontal frequency range as per the PLL section. These bits, PFR0,1 are presented at the

PLL interface as the signals ‘Free_run_freq0’, and ‘Free_run_freq1’.

Bit 2

Vertical Blank Disable. When this bit is set to 0, the internally generated vertical blanking pulse is OR’d with the

horizontal blank pulse internal to the logic core, to blank the video during retrace. When this bit is set to 1 (default) the

internal vertical blanking is disabled.

Bit 3

OSD Override. When this bit is 0 (default) normal video operation is assumed. When this bit is 1, the OSD select is

overridden, and OSD only is selected, preventing normal video from being displayed (used for ‘out-of-range’ condition).

Bit 4

Free Run Enable. When this bit is set to 0 (default), the PLL will be supplied with the H flyback synchronization pulse.

When set to 1, the H flyback pulse will be gated off.

Bit 5

Clamp Polarity. Determines the polarity of the clamp signal used by the LM1238. When this bit is 0 (default) the LM1238

requires a positive clamp signal. When this bit is 1, the LM1238 requires a negative going clamp signal.

Bit 6

Burn-in Screen Enable (BIS). When this bit is a ’1’, the burn-in screen is active and input video will be ignored. When

this bit is a ’0’ (default), the burn-in screen is disabled.

Bit 7

Interface. When this bit is set to 1, the jitter reduction circuit is set to alternate the phase every alternate field. When it

is set to 0 (default), normal progressive scan is assumed.

Software Reset and Test Control Register (I

Register Name (address): SRTSTCTRL (0x081Fh)

7

654321

0

RSV

RSV

RSV

RSV

RSV

RSV

RSV

SRST

Bit 0

Software Reset. Setting this bit causes a software reset. All registers (except this one) are loaded with their default

values. All operations currently in progress are aborted (except for I

when the reset has been completed.

Bits 1–7 Reserved.

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