TUSB320 datasheet(16/35 Pages) TI1

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TUSB320, TUSB320I

SLLSEN9C – MAY 2015 – REVISED SEPTEMBER 2016

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Table 7. CSR Registers Bit Address and Description (continued)

ADDRESS

BIT(S)

BIT NAME

DESCRIPTION

ACCESS

0x09

7:6

ATTACHED_STATE

This is an additional method to communicate attach other

than the ID pin. These bits can be read by the application to

determine what was attached.

00 – Not attached (default)

01 – Attached.SRC (DFP)

10 – Attached.SNK (UFP)

11 – Attached to an accessory

CABLE_DIR

Cable orientation. The application can read these bits for

cable orientation information.

0 – CC1

1 – CC2 (default)

INTERRUPT_STATUS

The INT pin is pulled low whenever a CSR changes. When

a CSR change has occurred this bit should be held at 1 until

the application clears it.

0 – Clear

1 – Interrupt (When INT_N is pulled low, this bit will be

1. This bit is 1 whenever any CSR are changed)

Note: SW must make sure the INTERRUPT_STATUS has

been cleared to zero. Rewrites to this register are needed

for the INT_N to be correctly asserted for all interrupt

events.

RCU

Reserved

2:1

DRP_DUTY_CYCLE

Percentage of time that a DRP advertises DFP during tDRP

00 – 30% (default)

01 – 40%

10 – 50%

11 – 60%

Reserved

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