ommended; one to V

signer may want to increase the value of the 33

Ω resistor at

pins 5, 8, and 11 for additional ESD protection at the video

inputs. Remember that the input capacitor to the video inputs

is also part of the DC restoration circuit. This circuit is de-

pending on a maximum circuit resistance of about 110

Ω. The

33

Ω resistors should not be increased in value. The designer

does have the option of decreasing the 10 µF video input ca-

pacitors down to 1 µF. The internal ESD protection and the

external clamp diodes, one to +12V and the other to ground,

will provide excellent ESD protection.

Interfacing to the OSD inputs is quite easy since the signal

processing necessary to match the OSD signals to the video

levels is done internally by the LM1283. However, proper de-

sign techniques must be followed in assuring that a good

TTL signal is received at the LM1283. Ground bounce in the

TTL signal can cause improper switching times, possibly

with multiple switching. Such affects will result in degradation

in the quality of the displayed OSD window. The final TTL

stage needs to be located near the LM1283 to assure clean

TTL signals. Propagation delay is another source capable of

degrading the OSD display. The optimum condition is to

have all OSD signals originate from one register, keeping the

variation in the propagation delays under 5 ns. If the OSD

feature is not used, or the lines may be disconnected for

some testing operations, then the Video/OSD Switch pin (pin

4) must have a pull down resistor to ground to insure opera-

tion in the video mode. Using a 47k pull down resistor will

keep this pin low, and provide enough resistance to where

the pin can still be driven directly by a TTL signal. Pins 1

through 3 should also be terminated the same way, eliminat-

ing the potential to switch logic levels just from the noise at

the open pins.

Figure 2 through Figure 4 show the timing diagrams for the

LM1283. When measuring propagation delays all TTL sig-

nals are measured at the time they cross 1.3V. The video

output is set to 4 V

the output is half way in its transition (changed by 2V). Rise

and fall times of the video output are measured between the

10% and 90% points of the transitions.

Board layout is always critical in a high frequency application

such as using the LM1283. A poor layout can result in ringing

of the video waveform after sudden transitions, or the part

could actually oscillate. A good ground plane and proper

routing of the +12V are important steps to a good PCB lay-

out. The LM1283 can operate on a single sided board with a

good layout. A ground plane is recommended and it is best to

isolate the output stage grounds from the rest of the circuit.

Also the two grounds should be connected together only at

one point, ideally where the ground cable is connected to the

board ground. Yes, all grounds are connected internally, but

trace resistance can still allow for ground bounce, giving

enough feedback for oscillations. The output stage power

supply pin, pin 22, does not have an internal connection to

the other power supply pins. This pin must be connected to

the +12V supply, preferably with high frequency isolation.

This is easily done with a ferrite bead between pin 22 and the

+12V supply.

Figure 8 and Figure 9 show the waveform ob-

tained with the LM1283 using the single sided demo board

designed for this part.

References

Zahid Rahim, “Guide to CRT Video Design,” Application

Note 861, National Semiconductor Corp., Jan. 1993

Ott, Henry W.

Noise Reduction Techniques in Electronic sys-

tems , John Wiley & Sons, New York, 1976

DS012684-22

FIGURE 8. LM1283 Rise Time

DS012684-23

FIGURE 9. LM1283 Fall Time

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