TPS54010 datasheet(13/25 Pages) TI

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C8 +

2pR1

(20)

ESR0 +

2pR

ESR

OUT

(21)

R2 +

0.891

OUT *

0.891

(11)

R5 +

2pC8

ESR

(22)

Z1 +

2pR3C6

(12)

Z2 +

2pR1C8

(13)

C7 +

7pR3

(23)

P1 +

2pR5C8

(14)

P2 +

2pR3C7

(15)

BIAS AND BOOTSTRAP CAPACITORS

INT +

2pR1C6

(16)

INT +

IN(MAX)

(17)

POWER GOOD

C6 +

2pR1

INT

(18)

R3 +

(19)

TPS54010

SLVS509A – MAY 2004 – REVISED AUGUST 2004

The closed-loop crossover frequency should be

chosen to be greater than fLC and less than one-fifth

of the switching frequency. Also, the crossover fre-

quency should not exceed 150 kHz, as the error

The first pole, fP1 is located to coincide with output

amplifier may not provide the desired gain. For this

filter ESR zero frequency. This frequency is given by:

design, a crossover frequency of 100 kHz was

chosen. This value is chosen for comparatively wide

loop bandwidth while still allowing for adequate phase

boost to insure stability.

where RESR is the equivalent series resistance of the

output capacitor.

Next, calculate the R2 resistor value for the output

voltage of 1.5 V using Equation 11:

In this case, the ESR zero frequency is 88.4 kHz, and

R5 can be calculated from:

For any TPS54010 design, start with an R1 value of

10 k

Ω. R2 is 14.7 kΩ.

The final pole is placed at a frequency above the

closed-loop crossover frequency high enough to not

Now, the values for the compensation components

cause the phase to decrease too much at the

that set the poles and zeros of the compensation

crossover frequency while still providing enough at-

network can be calculated. Assuming that R1 >> than

tenuation so that there is little or no gain at the

R5 and C6 >> C7, the pole and zero locations are

switching frequency. The fP2 pole location for this

given by Equation 12 through Equation 18:

circuit is set to 3.5 times the closed-loop crossover

frequency and the last compensation component

value C7 can be derived:

Note that capacitors are only available in a limited

range of standard values, so the nearest standard

value has been chosen for each capacitor. The

measured closed-loop response for this design is

Additionally, there is a pole at the origin, which has

shown in Figure 5.

unity gain at a frequency:

Every TPS54010 design requires a bootstrap capaci-

This pole is used to set the overall gain of the

tor, C3, and a bias capacitor, C4. The bootstrap

compensated error amplifier and determines the

capacitor must be a 0.1 µF. The bootstrap capacitor

closed-loop crossover frequency. Because R1 is

is located between the PH pins and BOOT. The bias

given as 1 k

Ω and the crossover frequency is

capacitor is connected between the VBIAS pin and

selected as 100 kHz, the desired fINT can be calcu-

AGND. The value should be 1.0 µF. Both capacitors

lated from Equation 17:

should be high-quality ceramic types with X7R or

X5R grade dielectric for temperature stability. They

should be placed as close to the device connection

pins as possible.

And the value for C6 is given by Equation 18:

The TPS54010 is provided with a power-good output

pin PWRGD. This output is an open-drain output and

is intended to be pulled up to a 3.3-V or 5-V logic

The first zero, fZ1 is located at one-half the output

supply. A 10-k

Ω pullup works well in this application.

filter LC corner frequency; so, R3 can be calculated

from:

The second zero, fZ2 is located at the output filter LC

corner frequency; so, C8 can be calculated from:

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