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ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

DISSIPATION RATINGS

(1) (2)

TPS54010

SLVS509A – MAY 2004 – REVISED AUGUST 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

OUTPUT VOLTAGE

PACKAGE

PART NUMBER

-40

°C to 85°C

Adjustible down to 0.9 V

TPS54010PWP

(1)

The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54010PWPR). See the application

section of the data sheet for PowerPAD drawing and layout information.

TPS54010

UNIT

SS/ENA, SYNC

–0.3 to 7

RT

–0.3 to 6

Input voltage range

VSENSE

–0.3 to 4

V

PVIN, VIN

–0.3 to 4.5

BOOT

–0.3 to 10

VBIAS, COMP, PWRGD

–0.3 to 7

Output voltage range

V

PH

–0.6 to 6

PH

Internally limited

Source current

COMP, VBIAS

6

mA

PH

25

A

Sink current

COMP

6

mA

SS/ENA, PWRGD

10

Voltage differential

AGND to PGND

±0.3

V

Operating junction temperature range

–40 to 125

°C

Storage temperature range

–65 to 150

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

300

°C

Human body model (HBM)

1.5

kV

Electrostatic Discharge (ESD) ratings

CDM

750

V

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

MIN

NOM

MAX

UNIT

Input voltage, VIN

3

4

V

Power Input voltage, PVIN

2.2

4

V

Operating junction temperature

–40

125

°C

THERMAL IMPEDANCE

PACKAGE

JUNCTION-TO-AMBIENT

POWER RATING

POWER RATING

POWER RATING

28-Pin PWP with solder

14.4

°C/W

3.81 W

2.77 W

28-Pin PWP without solder

27.9

°C/W

3.58 W

1.97 W

1.43 W

(1)

For more information on the PWP package, refer to TI technical brief, literature number SLMA002.

(2)

Test board conditions:

a. 3 inch x 3 inch, 4 layers, thickness: 0.062 inch

b. 1.5-oz. copper traces located on the top of the PCB

c. 1.5-oz. copper ground plane on the bottom of the PCB

d. 0.5-oz. copper ground planes on the 2 internal layers

e. 12 thermal vias (see Recommended Land Pattern in applications section of this data sheet)

(3)

Maximum power dissipation may be limited by over current protection.

2