TPS54010 datasheet(21/25 Pages) TI

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VOLTAGE REFERENCE

OSCILLATOR AND PWM RAMP

Switching Frequency +

100 kW

500 [kHz]

(27)

ERROR AMPLIFIER

DEAD-TIME CONTROL AND MOSFET

PWM CONTROL

TPS54010

SLVS509A – MAY 2004 – REVISED AUGUST 2004

External loading on VBIAS is allowed, with the

During this period, the PWM ramp discharges rapidly

caution that internal circuits require a minimum

to its valley voltage. When the ramp begins to charge

VBIAS of 2.7 V, and external loads on VBIAS with ac

back up, the low-side FET turns off and high-side

or digital-switching noise may degrade performance.

FET turns on. As the PWM ramp voltage exceeds the

The VBIAS pin may be useful as a reference voltage

error amplifier output voltage, the PWM comparator

for external circuits. VBIAS is derived from the VIN

resets the latch, thus turning off the high-side FET

pin; see the functional block diagram of this data

and turning on the low-side FET. The low-side FET

sheet.

remains on until the next oscillator pulse discharges

the PWM ramp. During transient conditions, the error

amplifier output could be below the PWM ramp valley

voltage or above the PWM peak voltage. If the error

The voltage reference system produces a precise Vref

amplifier is high, the PWM latch is never reset, and

signal by scaling the output of a temperature stable

the high-side FET remains on until the oscillator pulse

bandgap circuit. During manufacture, the bandgap

signals the control logic to turn the high-side FET off

and scaling circuits are trimmed to produce 0.891 V

and the low-side FET on. The device operates at its

at the output of the error amplifier, with the amplifier

maximum duty cycle until the output voltage rises to

connected as a voltage follower. The trim procedure

the regulation set-point, setting VSENSE to approxi-

adds

the

high-precision

regulation

the

mately the same voltage as VREF. If the error

TPS54010, because it cancels offset errors in the

amplifier output is low, the PWM latch is continually

scale and error amplifier circuits.

reset and the high-side FET does not turn on. The

low-side FET remains on until the VSENSE voltage

decreases

range

that

allows

the

PWM

comparator to change states. The TPS54010 is

The oscillator frequency is set to an internally fixed

capable of sinking current continuously until the

value of 350 kHz. The oscillator frequency can be

output reaches the regulation set-point.

externally adjusted from 280 to 700 kHz by con-

necting a resistor between the RT pin to ground. The

If the current limit comparator trips for longer than

switching frequency is approximated by the following

100 ns, the PWM latch resets before the PWM ramp

equation, where R is the resistance from RT to

exceeds the error amplifier output. The high-side FET

AGND:

turns off and low-side FET turns on to decrease the

energy in the output inductor and consequently the

output current. This process is repeated each cycle in

which the current limit comparator is tripped.

The high-performance, wide bandwidth, voltage error

DRIVERS

amplifier sets the TPS54010 apart from most dc/dc

converters. The user is given the flexibility to use a

Adaptive dead-time control prevents shoot-through

wide range of output L and C filter components to suit

current

from

flowing

both

N-channel

power

the particular application needs. Type-2 or Type-3

MOSFETs during the switching transitions by actively

compensation can be employed using external com-

controlling the turn-on times of the MOSFET drivers.

pensation components.

The high-side driver does not turn on until the voltage

at the gate of the low-side FET is below 2 V. While

the low-side driver does not turn on until the voltage

at the gate of the high-side MOSFET is below 2 V.

Signals from the error amplifier output, oscillator, and

The high-side and low-side drivers are designed with

current limit circuit are processed by the PWM control

300-mA source and sink capability to quickly drive the

logic. Referring to the internal block diagram, the

power MOSFETs gates. The low-side driver is sup-

control logic includes the PWM comparator, OR gate,

plied from VIN, whereas the high-side driver is

PWM latch, and portions of the adaptive dead-time

supplied from the BOOT pin. A bootstrap circuit uses

and control-logic block. During steady-state operation

an external BOOT capacitor and an internal 2.5-

Ω

below

the

current

limit

threshold,

the

PWM

bootstrap switch connected between the VIN and

comparator output and oscillator pulse train alter-

BOOT pins. The integrated bootstrap switch improves

nately reset and set the PWM latch. Once the PWM

drive efficiency and reduces external component

latch is set, the low-side FET remains on for a

count.

minimum duration set by the oscillator pulse width.

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