MIC45404 datasheet(22/32 Pages) MICROCHIP

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MIC45404

DS20005478A-page 22

 2015 Microchip Technology Inc.

5.7

Input Capacitor Selection

Two main requirements determine the size and

characteristics of the input capacitor:

• Steady-State Ripple

• RMS Current

The Buck Converter input current is a pulse train with

very fast rising and falling times, so low-ESR ceramic

capacitors are recommended for input filtering because

of their good high-frequency characteristics.

By assuming an ideal input filter (which can be assimi-

lated to a DC input current feeding the filtered buck

power stage) and by neglecting the contribution of the

input capacitor ESR to the input ripple (which is typically

possible for ceramic input capacitors), the minimum

capacitance value, CIN(MIN), needed for a given input

peak-to-peak ripple voltage,

Vr, IN, can be estimated as

shown in Equation 5-11:

EQUATION 5-11:

The RMS current, IIN,RMS, of the input capacitor is

estimated as in Equation 5-12:

EQUATION 5-12:

Note that, for a given output current, IO, worst-case

values are obtained at D = 0.5.

Multiple input capacitors can be used to reduce input

ripple amplitude and/or individual capacitor RMS

current.

5.8

Compensation Design

As a simple first-order approximation, the Valley Current

mode controlled buck power stage can be modeled as a

voltage controlled current source, feeding the output

capacitor and load. The inductor current state variable is

removed and the power stage transfer function from

COMP to the inductor current is modeled as a transcon-

ductance (GmPS). The simplified model of the control

loop is shown in Figure 5-3. The power stage trans-

conductance, GmPS, shows some dependence on

current levels and it is also somewhat affected by

process variations, therefore, some design margin is

recommended against the typical value, GmPS = 12.5A/V

(see Section 1.0 “Electrical Characteristics”).

FIGURE 5-3:

Simplified Small Signal

Model of the Voltage Regulation Loop.

This simplified approach disregards all issues related

to the inner current loop, like its stability and bandwidth.

This approximation is good enough for most operating

scenarios, where the voltage loop bandwidth is not

pushed to aggressively high frequencies.

Based on the model shown in Figure 5-3, the

control-to-output transfer function is:

EQUATION 5-13:

The MIC45404 module uses a transconductance

(GmEA = 1.4 mA/V) error amplifier. Frequency compen-

sation is implemented with a Type-II network (RC1, CC1

and CC2) connected from the COMP to AGND. The

compensator transfer function consists of an integrator

for zero DC voltage regulation error, a zero to boost the

phase margin of the overall loop gain around the

crossover frequency and an additional pole that can

be used to cancel the output capacitor ESR zero, or to

further attenuate switching frequency ripple. In both

cases, the additional pole makes the regulation loop

less susceptible to switching frequency noise. The

additional pole is created by capacitor CC2 (internally

provided, CC2 value is 47 pF). Equation 5-14 details the

compensator transfer function, HC(S) (from OUTSNS to

COMP).

IN MIN



–





V

r,IN



----------------------------------------

Where:

D is the duty cycle at the given operating point.

IN,RMS

–





GmPS

Gm Error

Amplifier

OUTSNS

COMP

REFDAC

VO Range

CC2

CC1

RC1

ESR

VIN

GmEA

CO S



-------------

 f



-----------------





 f



-----------------





--------------------------------



Where f

Z and fP = the frequencies associated with

the output capacitor ESR zero and with the load

pole, respectively:

 C

ESR



-------------------------------------

 C

ESR





-------------------------------------------------------

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