MIC45404 datasheet(23/32 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005478A-page 23

MIC45404

EQUATION 5-14:

The overall voltage loop gain, TV(S), is the product of

the control-to-output and the compensator transfer

functions:

EQUATION 5-15:

The value of the attenuation ratio, R1/(R1 + R2),

depends on the output voltage selection and can be

retrieved as illustrated in Table 5-5:

The compensation design process is as follows:

Set the TV(s) loop gain crossover frequency, fXO,

in the range of fS/20 to fS/10. Lower values of

fXO allow a more predictable and robust phase

margin. Higher values of fXO would involve addi-

tional considerations about the current loop

bandwidth in order to achieve a robust phase

margin. Taking a more conservative approach is

highly recommended.

EQUATION 5-16:

Select RC1 to achieve the target crossover

frequency, fXO, of the overall voltage loop. This

typically happens where the power stage

transfer function, GCO(S), is rolling off at

-20 dB/decade. The compensator transfer func-

tion, HC(S), is in the so-called midband gain

region, where CC1 can be considered a DC

blocking short circuit, while CC2 can still be

considered as an open circuit, as calculated in

Equation 5-17:

EQUATION 5-17:

Select capacitor CC1 to place the compensator

zero at the load pole. The load pole moves

around with load variations, so to calculate the

load pole use as a load resistance RL, the value

determined by the nominal output current, IO, of

the application, as shown in Equation 5-18 and

Equation 5-19:

EQUATION 5-18:

EQUATION 5-19:

Knowing that an internal CC2 capacitor of 47 pF

is provided already, find out if any additional

capacitance is needed to augment the overall

value of the capacitor, CC2.

The CC2 (total value) is intended for placing the com-

pensator pole at the frequency of the output capacitor

ESR zero and/or achieve additional switching

ripple/noise attenuation.

If the output capacitor is a polarized one, its ESR zero

will typically occur at low enough frequencies to cause

the loop gain to flatten out and not roll off at a

-20 dB/decade slope, around or just after the crossover

frequency, fXO. This causes undesirable scarce

compensation design robustness and switching noise

susceptibility. The compensator pole is then used to

cancel the output capacitor ESR zero and achieve a

well-behaved roll-off of the loop gain above the

crossover frequency.

If the output capacitors are only ceramic, then the ESR

zeros frequencies could be very high. In many cases,

the frequencies could even be above the switching

frequency itself. Loop gain roll-off at -20 dB/decade is

ensured well beyond the crossover frequency, but even

in this case, it is good practice to still make use of the

compensator pole to further attenuate switching noise,

while conserving phase margin at the crossover

frequency.

TABLE 5-5:

INTERNAL FEEDBACK

DIVIDER ATTENUATION

VALUES

VO Range

R1/(R1 + R2)

(A =1 +R2/R1)

0.7V-1.2V

1.5V-1.8V

0.5

2.5V(2.49V)-3.3V

0.333



---------------------Gm





--------------------------------------------



–







---------------------------







--------------------------------------------------------------------





CO S





------f

------



---------------------





 C



------------------------------------



-------

ESR





------------------------------------------

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