ADS8324

7

SBAS172A

www.ti.com

THEORY OF OPERATION

The ADS8324 is a classic Successive Approximation Reg-

ister (SAR) A/D converter. The architecture is based on

capacitive redistribution that inherently includes a sample-

and-hold function. The converter is fabricated on a 0.6

µ

CMOS process. The architecture and process allow the

ADS8324 to acquire and convert an analog signal at up to

50,000 conversions per second while consuming less than

The ADS8324 requires an external reference, an external

value of the reference voltage directly sets the range of the

analog input. The reference input current depends on the

conversion rate of the ADS8324.

The external clock can vary between 24kHz (1kHz through-

put) and 1.2MHz (50kHz throughput). The duty cycle of the

clock is essentially unimportant as long as the minimum

high and low times are at least 200ns. The minimum clock

frequency is set by the leakage on the capacitors internal to

the ADS8324.

The analog input is provided to two input pins: +In and –In.

When a conversion is initiated, the differential input on these

pins is sampled on the internal capacitor array. While a

conversion is in progress, both inputs are disconnected from

any internal function.

The digital result of the conversion is clocked out by the

DCLOCK input and is provided serially, most significant bit

is no pipeline delay. It is possible to continue to clock the

ADS8324 after the conversion is complete and to obtain the

serial data least significant bit first. See the digital timing

section for more information.

ANALOG INPUT

The analog input is bipolar and fully differential. There are

two general methods of driving the analog input of the

ADS8324: single-ended or differential, as shown in Figure

1. When the input is single-ended, the –In input is held at a

fixed voltage. The +In input swings around the same voltage

may vary, as shown in Figure 2.

When the input is differential, the amplitude of the input is

the difference between the +In and –In input, or, +In – (–In).

A voltage or signal is common to both of these inputs. The

common voltage. However, since the inputs are 180

° out-of-

phase, the peak-to-peak amplitude of the difference voltage

the voltage that may be common to both inputs, as shown in

Figure 3.

In each case, care should be taken to ensure that the output

impedance of the sources driving the +In and –In inputs are

matched. If this is not observed, the two inputs could have

FIGURE 1. Methods of Driving the ADS8324—Single-Ended

or Differential.

FIGURE 2. Single-Ended Input—Common Voltage Range

FIGURE 3. Differential Input—Common Voltage Range vs

ADS8324

ADS8324

Single-Ended Input

Common

Voltage

2 • V

REF

peak-to-peak

Differential Input

Common

Voltage

V

REF

peak-to-peak

V

REF

peak-to-peak

0.5

0.6

0.7

0.8

0.9

1

V

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

V

Single-Ended Input

0.5

0.6

0.7

0.8

0.9

1

V

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

V

Differential Input