CLC1003 datasheet(13/17 Pages) EXAR

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Rev 1D

CLC1003

0.5

1.5

-40

-20

100

120

Ambient Temperature (°C)

TSOT-6

SOIC-8

Figure 3. Maximum Power Derating

Driving Capacitive Loads

Increased phase delay at the output due to capacitive loading

can cause ringing, peaking in the frequency response, and

possible unstable behavior. Use a series resistance, RS,

between the amplifier and the load to help improve stability

and settling performance. Refer to Figure 4.

Input

Output

Figure 4. Addition of RS for Driving Capacitive Loads

The CLC1003 is capable of driving up to 300pF directly, with

no series resistance. Directly driving 500pF causes over

4dB of frequency peaking, as shown in the plot on page 6.

Table 1 provides the recommended RS for various capacitive

loads. The recommended RS values result in ≤ 1dB peaking

in the frequency response. The Frequency Response vs.

CL plots, on page 6, illustrate the response of the CLC1003.

CL (pF)

RS (Ω)

-3dB BW (MHz)

500

1000

7.5

3000

Table 1: Recommended RS vs. CL

For a given load capacitance, adjust RS to optimize the

tradeoff between settling time and bandwidth. In general,

reducing RS will increase bandwidth at the expense of

additional overshoot and ringing.

Overdrive Recovery

An overdrive condition is defined as the point when either

one of the inputs or the output exceed their specified

voltage range. Overdrive recovery is the time needed for the

amplifier to return to its normal or linear operating point. The

recovery time varies based on whether the input or output

is overdriven and by how much the ranges are exceeded.

The CLC1003 will typically recover in less than 20ns from

an overdrive condition. Figure 5 shows the CLC1003 in an

overdriven condition.

-2

-1

-3

-2

-1

0.25

0.5

0.75

1.25

1.5

1.75

Time (us)

Output

Input

VIN = .8Vpp

G = 5

Figure 5: Overdrive Recovery

Considerations for Offset and Noise Performance

Offset Analysis

There are three sources of offset contribution to consider;

input bias current, input bias current mismatch, and input

offset voltage. The input bias currents are assumed to be

equal with and additional offset current in one of the inputs

to account for mismatch. The bias currents will not affect

the offset as long as the parallel combination of Rf and Rg

matches Rt. Refer to Figure 6.

+Vs

-Vs

–

CLC1003

Figure 6: Circuit for Evaluating Offset

The first place to start is to determine the source resistance.

If it is very small an additional resistance may need to be

added to keep the values of Rf and Rg to practical levels.

For this analysis we assume that Rt is the total resistance

present on the non-inverting input. This gives us one

equation that we must solve:

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