SN54ALS161B, SN54ALS163B, SN54AS161, SN54AS163

SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163

SYNCHRONOUS 4-BIT BINARY COUNTERS

SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986

POST OFFICE BOX 655303

5

typical clear, preset, count, and inhibit sequences

0

3

2

1

14

13

12

Outputs

Data

Inputs

RCO

QD

QC

QB

QA

ENT

ENP

CLK

D

C

B

A

LOAD

CLR

’ALS161B, ’AS161, ’ALS163B, ’AS163

Illustrated below is the following sequence:

1. Clear outputs to zero (’ALS161B and ’AS161 are asynchronous; ’ALS163B and ’AS163 are synchronous)

2. Preset to binary twelve

3. Count to thirteen, fourteen, fiften, zero, one, and two

4. Inhibit

Async

Clear

Preset

Sync

Clear

Inhibit

Count