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MCP3918 Datasheet(PDF) 48 Page - Microchip Technology

Part # MCP3918
Description  3V Single-Channel Analog Front End
PDF  88 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3918 Datasheet(HTML) 48 Page - Microchip Technology

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MCP3918
DS20005287A-page 48
 2014 Microchip Technology Inc.
6.5.1
CONTINUOUS READ
The STATUSCOM register contains the loop settings
for the internal register address pointer (READ<1:0>
bits and WRITE bit). For the Continuous Read modes,
the address selection can take the four following
values:
No SDI data coming after the Control byte is
considered during a continuous read communication.
The following figures represent a typical, continuous
read
communication
with
the
default
settings
(READ<1:0> = 10, WIDTH_DATA<1:0> = 01) for SPI
Mode 0,0 (Figure 6-7) and SPI Mode 1,1 (Figure 6-8).
In SPI Mode (1,1), the SDO pin stays in the last state
(LSB of previous data) after a complete reading, which
also allows seamless Continuous Read mode (see
Figure 6-8).
FIGURE 6-7:
Typical Continuous Read Communication (WIDTH_DATA<1:0> = 01, SPI Mode 0,0).
FIGURE 6-8:
Typical Continuous Read Communication (WIDTH_DATA<1:0> = 01, SPI Mode 1,1).
TABLE 6-1:
ADDRESS SELECTION IN
CONTINUOUS READ
READ<1:0>
Register Address Set Grouping
for Continuous Read
Communications
00
Static (No incrementation)
01
Groups
10
Types (Default)
11
Full Register Map
Note:
For continuous reading of ADC data in
SPI Mode 0,0 (see Figure 6-7), once the
data has been completely read after a
data ready pulse, the SDO pin will take the
MSB value of the previous data at the end
of the reading (falling edge of the last SCK
clock). If SCK stays idle at logic low (by
definition of Mode 0,0), the SDO pin will
be updated at the falling edge of the next
Data Ready pulse (synchronously with the
DR pin falling edge with an output timing
of tDODR) with the new MSB of the data
corresponding to the Data Ready pulse.
This mechanism allows the MCP3918 to
continuously read ADC data outputs
seamlessly, even in SPI Mode (0,0).
Don’t care
SCK
SDI
SDO
CS
Hi-Z
8x
0x01
24x
Starts read sequence at
address 00000
24x
Don’t care
DR
Complete READ sequence on
new ADC output channel
Complete READ sequence on
the ADC output channel
DATA_CH0
Stays at
DATA_CH<0>
DATA_CH0
Don’t care
SCK
SDI
SDO
CS
Hi-Z
8x
0x01
24x
Starts read sequence at
address 00000
24x
Don’t care
DATA_CH0
DATA_CH0
DATA_CH0
<23>
New data
DATA_CH0
<23>
Old data



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