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MICRF229 Datasheet(PDF) 11 Page - Micrel Semiconductor

Part # MICRF229
Description  400MHz to 450MHz ASK/OOK Receiver with Auto-Poll and RSSI
PDF  23 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

MICRF229 Datasheet(HTML) 11 Page - Micrel Semiconductor

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Micrel, Inc.
MICRF229
April 15, 2015
11
Revision 1.0
There are eight selectable low-pass filter BW settings:
1625Hz, 3250Hz, 6500Hz, 11000Hz, 13000Hz, 19000Hz,
34000Hz and 46000Hz for 433.92MHz operation. The
low-pass filter BW is directly proportional to the crystal
reference
frequency,
and
hence
RF
Operating
Frequency. Filter BW values can be easily calculated by
direct scaling. Equation 5 illustrates filter Demod BW
calculation:
BWOperating Freq = BW@433.92MHz ×
433.92
(MHz)
Freq
Operating
Eq. 5
It is very important to select a suitable low-pass filter BW
setting for the required data rate to minimize bit error
rate.
Use the sensitivity curves that show BER vs. bit
rates for different D[16:4:3] settings as a guide.
This low-pass filter
−3dB corner frequency bandwidth can
be configured by setting the registers as in Table 1 for
433.92MHz.
Table 1. Low-Pass Filter Bandwidth Selection @ 434MHz RF
Input
D[16]
D[4]
D[3]
Low-Pass
Filter BW
Maximum
Encoded Bit Rate
0
0
0
1625Hz
2.5KBps
0
0
1
3250Hz
5KBps
0
1
0
6500Hz
10KBps
0
1
1
13000Hz
20KBps
1
0
0
11000Hz
Do Not Use
1
0
1
19000Hz
1
1
0
34000Hz
1
1
1
46000Hz
Bit rate refers to the encoded bit rate. Encoded bit rate is
1/(shortest pulse duration) that appears at DO, as
illustrated in Figure 2.
Figure 2. Transmitted Bit Rate through the Air
Alternatively the default registers setting for D[16:4:3] is
011 at power up, without programming the setting of
these bits, the demodulation bandwidth can be selected
externally by SEL1 pin.
Table 2. Demod Bandwidth
− SEL1 External Input
SEL1
Bandwidth at 434MHz
0
3250Hz – D3,D4 must be 11
1
13000Hz – default internal pull up
Slicer and CTH
The signal prior to the slicer, labeled “Audio Signal” in the
Functional Diagram, is still baseband analog signal. The
data slicer converts the analog signal into ones and zeros
based on 50% of the slicing threshold voltage built up in
the CTH capacitor. After the slicer, the signal is
demodulated OOK digital data. When there is only
thermal noise at ANT pin, the voltage level on CTH pin is
about 650mV. This voltage starts to drop when there is
RF signal present. When the RF signal level is greater
than
−100dBm, the voltage is about 400mV.
The value of the capacitor from CTH pin to GND is not
critical to the sensitivity of MICRF229, although it should
be large enough to provide a stable slicing level for the
comparator. The value used in the evaluation board of
0.1μF is good for all bit rates from 500bps to 40kbps.
The data slice level can be set by programming D[6:5]
bits, which also has the effect on the sensitivity of the
receiver as indicated in the sensitivity graphs.
Table 3. Slice Level
− Serial Register Control
D6
D5
Mode
0
0
Slice level 60%
0
1
Slice level 30%
1
0
Slice level 40%
1
1
Slice level 50% - default
CTH Hold Mode
If the internal demodulated signal (DO in the Functional
Diagram) is at logic LOW for more than about 4msec, the
chip automatically enters CTH hold mode, which holds
the voltage on CTH pin constant even without RF input
signal. This is useful in a transmission gap, or “dead
time”, used in many encoding schemes. When the signal
reappears, CTH voltage does not need to re-settle,
improving the time to output with no pulse width
distortion, or time to good data (TTGD).



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