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VSC8122 Datasheet(PDF) 3 Page - Vitesse Semiconductor Corporation |
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VSC8122 Datasheet(HTML) 3 Page - Vitesse Semiconductor Corporation |
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3 / 14 page ![]() VITESSE SEMICONDUCTOR CORPORATION Multi-Rate SONET/SDH Clock and Data Recovery IC Data Sheet VSC8122 G52228-0, Rev 4.1 Page 3 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Outputs can also be AC terminated as shown in Figure 3. The output differential voltage and common-mode voltage range are specified in Table 4, High-Speed Inputs and Outputs. Figure 3: High-Speed Clock and Data Output AC Termination Clock Recovery The VSC8122 has a selectable input data rate. Two pins (FSEL0 and FSEL1) select the data rate to be pro- vided to the VSC8122. Table 1: Input Data Rate Select The incoming data is presented both to the clock recovery circuit and the data retiming circuit. When there is a phase error between the incoming data and the on-chip Voltage-Controlled Oscillator (VCO), the loop filter raises or lowers the control voltage of the VCO to null the phase difference. The lock detector monitors the frequency difference between the REFCK (optionally divided by a pres- caler) and the recovered clock divided by 128. In the event of the loss of an input signal, or if the input is switch- ing randomly, the VCO will move in one direction. At the time the VCO differs by more than 1MHz from the REFCK based 2.48832GHz rate, the lock detector will assert the LOL output. LOL is designed to be asserted from between 2.3µs and 100µs after the interruption of data. The VCO will continue to be frequency-locked at approximately 1MHz off of the REFCK based 2.48832GHz rate. When NRZ data is again presented at the data input, the phase detector will permit the VCO to lock to the incoming data. Hysteresis is provided which delays the deassertion of LOL until approximately 160µs following the restoration of valid data. The NOREF output will go high to indicate that there is no signal on the REFCK input, or that the REFCK is more than approximately 25% above or below the expected value. Input Data Rate FSEL0 FSEL1 2.48832Gb/s or 2.5Gb/s 00 1.24416Gb/s or 1.25Gb/s 10 622.08Mb/s or 625Mb/s 01 155.52Mb/s or 156.25Mb/s 11 VSC8122 Zo = 50Ω Zo = 50Ω VTERM VTERM VCC VCC 50 Ω 50 Ω 100 Ω 100 Ω CO+ / DO+ CO- / DO- 0.1 µF 0.1 µF |
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