82P33741 datasheet(13/61 Pages) IDT

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Revision 6, July 21, 2016

82P33741 Datasheet

2.2

RESET OPERATION

The device must be reset properly in order to ensure operations conform with specification.

To properly reset the device, the RSTB pin must be held at a low value for at least 50 usec. The device should be brought out of reset only at the

time when power supplies are stabilized and the system clock is available on OSCi pin. The RSTB can be held low until this time, or pulsed low for at

least 50us after this time.

The bootstrap pins (XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:1], SONET/SDH) need to be held at desired states for at least 2ms after de-

assertion of RSTB pin to allow correct sampling. See Figure 3 for detail.

If loading from an EEPROM, the maximum time from RSTB de-assert to have stable clocks is 100ms. Note that if there is a bad EEPROM read

sequence and the EEPROM loading is repeated once or twice (three times halts the device), then this time can be 2 or 3 times longer respectively. If

not loading from EEPROM the maximum time from RSTB de-assert to have stable clocks is 10ms.

An on-board reset circuit or a commercially available voltage supervisory can be used to generate the reset signal. It is also feasible to use a

standalone power-up RC reset circuit. When using a power-up RC reset circuit, careful consideration must be taken into account to fine tune the

circuit properly based on each power supply's specification to ensure the power supply rise time is fast enough with respect to the RC time constant

of the RC circuit.

Figure 3. Reset timing diagram

VDDD

VDDA

OSCI

RSTB

50 s

2ms

Bootstrap

Pins*

* Bootstrap pins are: XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:1], SONET/SDH

82P33741 Datasheet(PDF) 13 Page - Integrated Device Technology