UCS81003 datasheet(97/108 Pages) MICROCHIP

97 / 108 page

 2014 Microchip Technology Inc.

DS20005334A-page 97

UCS81003

11.2.1.3

SMBus Data Bytes

All SMBus data bytes are sent most significant bit first

and composed of eight bits of information.

11.2.1.4

SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that

it receives. This is done by the client device pulling the

SMBus data line low after the 8th bit of each byte that is

transmitted. This applies to both the Write Byte and

Block Write protocols.

By holding the SMBus data line high after the 8th data

bit

has

been

sent,

the

host

will

NACK

(not

acknowledge) the last data byte to be received from the

client. For the Block Read protocol, the host will ACK

each data byte that it receives except the last data byte.

11.2.1.5

SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the

SMBus data line from a logic ‘0’ state to a logic ‘1’

state while the SMBus clock line is in a logic ‘1’ state.

When the UCS81003 detects an SMBus Stop bit, and

it has been communicating with the SMBus protocol,

it will reset its client interface and prepare to receive

further communications.

11.2.1.6

SMBus Timeout and Idle Reset

The UCS81003 includes an SMBus timeout feature. If the

clock is held at logic ‘0’ for tTIMEOUT, the device can time-

out and reset the SMBus interface. The SMBus interface

can also reset if both the clock and data lines are held at

a logic ‘1’ for tIDLE_RESET. Communication is restored with

a Start condition. This functionality defaults to disabled

and can be enabled by clearing the DIS_TO bit in the

Emulation Configuration register (Register 10-9).

11.2.2

SMBUS AND I2C COMPATIBILITY

The major differences between SMBus and I2C devices

are highlighted in this section. For more information,

refer to the SMBus 2.0 and I2C specifications.

• UCS81003 supports I2C fast mode at 400 kHz.

This covers the SMBus maximum time of 100 kHz.

• Minimum frequency for SMBus communications

is 10 kHz.

• The SMBus client protocol will reset if the clock is

held at a logic ‘0’ for longer than 30 ms. This time-

out functionality is disabled by default in the

UCS81003 and can be enabled by clearing the

DIS_TO bit. I2C does not have a timeout.

• Except when operating in Sleep mode, the

SMBus client protocol will reset if both the clock

and data lines are held at a logic ‘1’ for longer

than 200 µs (idle condition). This function is

disabled by default in the UCS81003 device and

can be enabled by clearing the DIS_TO bit. I2C

does not have an idle condition.

•I2C devices do not support the Alert Response

Address functionality (which is optional for SMBus).

•I2C devices support block read and write

differently. I2C protocol allows for unlimited

number of bytes to be sent in either direction. The

SMBus protocol requires that an additional data

byte indicating number of bytes to read/write is

transmitted. The UCS81003 supports I2C

formatting only.

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