ESDALC6V1W5

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With the focus of lowering the operation levels, the problem of malfunction caused by the environment is

critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems.

As a transient voltage suppressor, ESDALC6V1W5 is an ideal choice for ESD protection by suppressing

ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is

prevented on the device protected by ESDALC6V1W5.

ESDALC6V1W5 serves as a parallel protection elements, connected between the signal line and ground.

As the transient rises above the operating voltage of the device, the ESDALC6V1W5 becomes a low

impedance path diverting the transient current to ground.

The clamping voltage is given by the following formula:

As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor.

1. ESD protection by ESDALC6V1W5

TECHNICAL INFORMATION

Rd

V(i/o)

R

L O

AD

Device

to be

protected

ESD surge

ESDALC6V1W5

Fig. A1: ESD clamping behavior

To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical

resistance value Rd. By taking into account the following hypothesis:

Rg > Rd and Rload > Rd

we have:

()

Vi o

V

R

V

R

BR

d

g

g

/

=+

×

The results of the calculation done Vg = 8kV, Rg = 330

Rd = 1.1

Ω (typ.) give:

()

V i o

Volts

/,

= 32 8

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be a few

tenths of volts during a few ns at the Vi/o side.