CS8411 datasheet(5/38 Pages) CIRRUS

5 / 38 page

CS8411 CS8412

DS61F1

SWITCHING CHARACTERISTICS - SERIAL PORTS

(TA = 25 °C for suffixes '-CP' and '-CS'; TA = -40 to 85 °C for suffixes '-IP' and '-IS';

VD+, VA+ = 5V ± 10%; Inputs: Logic 0 = DGND, logic 1 = VD+; CL = 20 pF)

6. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part.

(A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods in

one audio sample. In Slave mode, exactly 32 SCK periods per audio sample must be provided in most

serial port formats. Therefor, if SCK is 128 x Fs, then SCK must be gated to provide exactly 32 periods

per audio sample.

7. In master mode SCK and FSYNC are outputs. In Slave mode they are inputs. In the CS8411, control

reg. 2 bit 1, MSTR, selects master. In the CS8412, formats 1, 3 and 9 are slaves.

8. The table above assumes data is output on the falling edge and latched on the rising edge. With the

CS8411 the edge is selectable. The table is defined for the CS8411 with control reg. 2 bit 0, SCED, set

to one, and for the CS8412 in formats 2, 3, 5, 6 and 7. For the other formats, the table and figure edges

must be reversed (i.e.. "rising" to "falling" and vice versa).

Parameter

Symbol

Min

Typ

Max

Unit

SCK Frequency

Master Mode Notes 6, 7

Slave Mode

Note 7

fsck

OWRx32

128xFs

SCK falling to FSYNC delay

Master Mode Notes 7, 8

tsfdm

-20

SCK Pulse Width Low

Slave Mode

Note 7

tsckl

SCK Pulse Width High

Slave Mode

Note 7

tsckh

SCK rising to FSYNC edge delay

Slave Mode

Notes 7,8

tsfds

FSYNC edge to SCK rising setup

Slave Mode

Notes 7,8

tfss

SCK falling (rising) to SDATA valid

Note 8

tssv

C, U, CBL valid to FSYNC edge

CS8412

Note 8

tcuvf

1/fsck

MCK to FSYNC edge delay

FSYNC from RXN/RXP

tmfd

sfds

ssv

SDATA

SCK

FSYNC

fss

MSB

sckh

ssv

sckl

SDATA

SCK

FSYNC

MSB

(Mode 1)

(Mode 3)

sfdm

ssv

cuvf

SDATA

SCK

FSYNC

C, U

Serial Output Timing - Slave Mode

Serial Output Timing -

Master Mode & C, U Port

FSYNC Generated From

Received Data

FSYNC

mfd

MCK

fss

sfds

sckh

sckl

SCK

(Modes 2,3,5,6,

7,10,12, and 13)

(Modes 0,1,4,

8,9, and 11)

CS8411 Datasheet(PDF) 5 Page - Cirrus Logic

CS8411 Datasheet(HTML) 5 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL