CAT5419

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8

Acknowledge Polling

The disabling of the inputs can be used to take advantage

of the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write operation, the

CAT5419 initiates the internal write cycle. ACK polling can

be initiated immediately. This involves issuing the start

condition followed by the slave address. If the CAT5419 is

still busy with the write operation, no ACK will be returned.

If the CAT5419 has completed the write operation, an ACK

will be returned and the host can then proceed with the next

instruction operation.

Write Protection

The Write Protection feature allows the user to protect

against inadvertent programming of the non-volatile data

registers. If the WP pin is tied to LOW, the data registers are

protected and become read only. Similarly, WP pin going

LOW after Start will interrupt non-volatile write to data

registers, while WP pin going LOW after internal write

cycle has started will have no effect on any write operation.

The CAT5419 will accept both slave addresses and

instructions, but the data registers are protected from

programming by the device’s failure to send an

acknowledge after data is received.

Figure 6. Slave Address Bits

* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

A0

A1

A2

A3

1

0

1

0

CAT5419

Figure 7. Write Timing

S

A

C

K

A

C

K

DR1 WCR DATA

S

T

O

P

P

BUS ACTIVITY:

MASTER

S

T

A

R

T

A

C

K

SLAVE

ADDRESS

INSTRUCTION

BYTE

Fixed

Variable

SDA LINE

INSTRUCTIONS AND REGISTER DESCRIPTION

Instructions

Slave Address Byte

The first byte sent to the CAT5419 from the master/

processor is called the Slave Address Byte. The most

significant four bits of the slave address are a device type

identifier. These bits for the CAT5419 are fixed at 0101[B]

(refer to Figure 8).

The next four bits, A3 − A0, are the internal slave address

and must match the physical device address which is defined

by the state of the A3 − A0 input pins for the CAT5419 to

successfully continue the command sequence. Only the

device which slave address matches the incoming device

address sent by the master executes the instruction. The A3

− A0 inputs can be actively driven by CMOS input signals

Instruction Byte

The next byte sent to the CAT5419 contains the

instruction and register pointer information. The four most

significant bits used provide the instruction opcode I [3:0].

The R1 and R0 bits point to one of the four data registers of

each associated potentiometer. The least two significant bits

point to one of two Wiper Control Registers. The format is

shown in Figure 9.

Table 11. DATA REGISTER SELECTION

Data Register Selected

R1

R0

DR0

0

0

DR1

0

1

DR2

1

0

DR3

1

1