LM2637 datasheet(11/17 Pages) NSC

11 / 17 page

Applications Information (Continued)

For a given current limit value, the minimum R

SENSE is deter-

mined by:

(4)

where V

OCP is the over-current trip voltage and is typically

55 mV, see the

Electrical Characteristic table. For example,

for a 20A current limit, the minimum R

SENSE is 2.75 mΩ.Ifa

Ω sense resistor is used instead, use appropriate values

of R

1 and R2 to make the voltage across R1 to be VOCP when

the voltage across R

SENSE is 60 mV.

The discrete current sense resistor usually has a very good

temperature coefficient and tolerance. A temperature coeffi-

cient of ±30 ppm/˚C is typical. Tolerance is usually ±1% or

±5%. Vishay Dale and IRC offer a broad range of discrete

sense resistors.

A PCB etch resistor can also be used as the R

SENSE. The

advantage of that approach is flexible resistance, which will

result in minimum power loss. R

1 and R2 may also be elimi-

nated. The drawback is too high a temperature coefficient,

typically +4000 ppm/˚C, which will result in a much less ac-

curate current limit than a discrete sense resistor. The cop-

per thickness of a PCB is usually of 5% tolerance.

Linear Section — There is no current limit function in the lin-

ear controllers. However, if there is ever a severe over-load,

the output voltage may drop below 0.63V, in which case the

under-voltage latch-off will provide the protection.

DESIGN CONSIDERATIONS

Control Loop Compensation

Switching Section — A switching regulator should be prop-

erly compensated to achieve a stable operation, tight regula-

tion and good dynamic performance. For a synchronous

buck regulator that needs to meet stringent load transient re-

quirement such as that of processor core voltage supply, a

2-pole-1-zero compensation network should suffice, such as

the one shown in

Figure 6 (C

1,C2,R1 and R2). This is be-

cause the ESR zero of the typical output capacitors is low

enough to make the control-to-output transfer function a

single-pole roll-off.

As an example, let us figure out the values of the compensa-

tion network components in

Figure 6. Assume the following

parameters: R = 20

Ω,R

L = 20 mΩ,RC = 9mΩ,L = 2 µH, C

= 7.5 mF, V

IN = 5V, Vm = 2V and PWM frequency = 300 kHz.

Notice R

L is the sum of the inductor DC resistance and the

on resistance of the FET’s.

The control-to-output transfer function is:

(5)

The ESR zero frequency is:

(6)

The double pole frequency is:

(7)

The corresponding Bode plots are shown in

Figure 7.

Notice since the ESR zero frequency is so low that the phase

doesn’t even go beyond −90˚. This makes the compensation

easier to do.

Since the DC gain and cutoff frequency (0 dB frequency) are

too low, some compensation is needed. Otherwise the low

DC gain will cause a poor line regulation, and the low cutoff

frequency may hurt transient response performance.

The transfer function for the 2-pole-1-zero compensation

network shown in

Figure 6 is:

(8)

where

(9)

One of the poles is located at origin to help achieve the high-

est DC gain. So there are three parameters to determine, the

position of the zero, the position of the second pole, and the

constant A. To determine the cutoff frequency and phase

margin, the loop bode plots need to be generated. The loop

transfer function is:

TF = −TF1 x TF2

(10)

By choosing the zero close to the double pole position and

the second pole to half of the switching frequency, the closed

loop transfer function turns out to be very good.

DS100848-9

FIGURE 5. Current Limit via Current Sense Resistor

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