That is, if f

−6

ΩF,

then the cutoff frequency will be 50 kHz, the phase margin

will be 72˚, and the DC gain will be that of the error amplifier.

See

Figure 8.

The compensation network component values can be deter-

mined by

Equation (9), since the values of f

now known. To more conveniently calculate the values,

Equation (9) can be rearranged as follows:

(11)

Notice there are three equations but four variables. So one

of the variables can be chosen arbitrarily. Since the current

driving capability of the error amplifier is limited to around 3

mA, it is a good idea to have a high impedance path from

EAO to FB. From

Equation (11) it can be told that a larger R

2

will result in a smaller C

show that the following combination is a good one: R

51

Ω,C

For a different application or different type of output capaci-

tors, a different compensation scheme may be necessary.

The user can either follow the steps above to figure the ap-

propriate component values or contact National for help.

Linear Section — The linear section is designed for high con-

trol bandwidth operation. The phase margin and cutoff fre-

quency depends on the external N-FET, output capacitors

and their ESR. As a rule of thumb, the designer can choose

any capacitance from 50 µF to 4000 µF, with a total ESR of

10 m

Ω to 100 mΩ. The larger the capacitance, the lower the

bandwidth. The above capacitors usually result in a control

bandwidth of 250 kHz to 1.2 MHz.

DS100848-17

FIGURE 6. Buck Converter from a Control Viewpoint

DS100848-18

FIGURE 7. Control-to-Output Bode Plots

DS100848-19

FIGURE 8. Loop Bode Plots

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