9FGL02 datasheet(9/19 Pages) IDT

9 / 19 page

OCTOBER 18, 2016

2-OUTPUT 3.3V PCIE CLOCK GENERATOR

9FGL02 DATASHEET

Electrical Characteristics–Current Consumption

Electrical Characteristics– REF

TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

IDDAOP

VDDA, All outputs active @100MHz

IDDOP

All VDD, except VDDA, All outputs active

@100MHz

IDDAPD

VDDA, DIF outputs off, REF output running

0.7

1.5

IDDPD

All VDD, except VDDA,

DIF outputs off, REF output running

8.8

IDDAPD

VDDA, all outputs off

0.7

1.5

IDDPD

All VDD, except VDDA, all outputs off

4.7

1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)

Powerdown Current

(Power down state and

Byte 3, bit 5 = '0')

Operating Supply Current

Wake-on-LAN Current

(Power down state and

Byte 3, bit 5 = '1')

TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Long Accuracy

ppm

see Tperiod min-max values

ppm

1,2

Clock period

Tperiod

REF output

High output Voltage

VHIGH

IOH = -2mA

0.8xVDDREF

Low output Voltage

VLOW

IOL = 2mA

0.2xVDDREF

trf1

Byte 3 = 1F, VOH = 0.8*VDD, VOL = 0.2*VDD

0.5

0.9

1.2

V/ns

trf1

Byte 3 = 5F, VOH = 0.8*VDD, VOL = 0.2*VDD

1.0

1.5

2.0

V/ns

1,3

trf1

Byte 3 = 9F, VOH = 0.8*VDD, VOL = 0.2*VDD

1.5

2.2

2.6

V/ns

trf1

Byte 3 = DF, VOH = 0.8*VDD, VOL = 0.2*VDD

2.0

2.9

3.2

V/ns

Duty Cycle

dt1X

VT = VDD/2 V

50.2

1,4

Duty Cycle Distortion

dtcd

VT = VDD/2 V

-1

1,5

Jitter, cycle to cycle

tjcyc-cyc

VT = VDD/2 V

150

1,4

tjdBc1k

1kHz offset

-145

-135

dBc

1,4

tjdBc10k

10kHz offset to Nyquist

-150

-140

dBc

1,4

tjphREF

12kHz to 5MHz, DIF SSC Off

0.13

0.3

ps (rms)

1,4

tjphREF

12kHz to 5MHz, DIF SSC On

1.5

ps (rms)

1,4

1Guaranteed by design and characterization, not 100% tested in production.

3 Default SMBus Value

4 When driven by a crystal.

5 When driven by an external oscillator via the X1 pin, X2 should be floating.

Noise floor

Jitter, phase

2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz

Rise/Fall Slew Rate

9FGL02 Datasheet(PDF) 9 Page - Integrated Device Technology

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