VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC870

High Performance Serial

Backplane Transceiver

G52190-0, Rev 4.1

Page 35

01/05/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

DC Characteristics

Table 5: LVDS and TTL Inputs and Outputs

Hot Swap

The LVDS input and output buffers are subject to hot swap events while being connected and disconnected from

the passive backplane. If the input is powered down but still receiving a signal from an output, the input must tolerate

extra input current and power. If the input is powered up but has no input connection, it will go to a valid logic state.

The table below lists the LVDS I/O parameters that relate to hot swap condition.

Table 6: Hot Swap LVDS I/O Parameters

Parameters

Description

Min

Typ

Max

Units

Conditions

Output HIGH voltage (TTL)

2.4

——

Output LOW voltage (TTL)

——

0.4

V

O/P Common Mode Range (LVDS)

1.2

—

2.1

V

At Min

∆V

OUT

∆V

OUT

Differential Output Voltage (LVDS)

400

—

1000

mV

100

Ω across input

I/P Common Mode Range (LVDS)

0.8

—

2.5

V

At Min

∆V

IN

∆V

IN

Differential Input Voltage (LVDS)

200

—

1600

mV

—

Input HIGH voltage (TTL)

2.0

—

V

—

Input LOW voltage (TTL)

0

—

0.8

V

—

Input HIGH current (TTL)

——

500

µAV

Input LOW current (TTL)

- 50

——

µAV

Parameters

Description

Value

Units

Conditions

LVDS maximum current delivered per output pin

10

mA

Normal Operation

LVDS maximum current allowed per input pin

40

mA

LVDS maximum added power per output pin

60

mW

LVDS input default logic state

LOW

—

Input Open