TPS65011 datasheet(38/52 Pages) TI

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TPS65011

SLVS501 – FEBRUARY 2004

Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active

due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before

unmasking the interrupt source.

If an interrupt condition occurs, then the INT pin is set low. The CHGSTATUS, REGSTATUS, and DEFGPIO

registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the

corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically

acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant

bit(s). No interrupt should be missed during the read process since this process starts by latching the contents of

the register before shifting them out at SDAT. Once the contents have been latched (takes a couple of

nanoseconds), the register is free to capture new interrupt conditions. Hence, the probability of missing anything

is, for practical purposes, zero.

The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:

•

CHGSTATUS(5,0) are positive edge set. Read of set CHGSTATUS(5,0) bits sets ACKINT1(5,0) bits.

•

CHGSTATUS(7-6,4-1) are level set. Read of set CHGSTATUS(7-6,4-1) bits sets ACKINT1(7-6,4-1) bits.

•

CHGSTATUS(5,0) clear when input signal low, and ACKINT1(5,0) bits are already set.

•

CHGSTATUS(7-6,4-1) clear when input signal is low.

•

ACKINT1(7-0) clear when CHGSTATUS(7-0) is clear.

•

REGSTATUS(7-5) are positive edge set. Read of set REGSTATUS(7-5) bits sets ACKINT2(7-5) bits.

•

REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.

•

REGSTATUS(7-5) clear when input signal low, and ACKINT1(7-5) bit are already set.

•

REGSTATUS(3-0) clear when input signal is low.

•

ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.

The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not

usually written to by the CPU since the TPS65011 internally sets/clears these registers:

•

ACKINT1(7:0) - Bit is set when the corresponding CHGSTATUS set bit is read via I2C.

•

ACKINT1(7:0) - Bit is cleared when the corresponding CHGSTATUS set bit clears.

•

ACKINT2(7:0) - Bit is set when the corresponding REGSTATUS set bit is read via I2C.

•

ACKINT2(7:0) - Bit is cleared when the corresponding REGSTATUS set bit clears.

•

ACKINT1(7:0) - a bit set masks the corresponding CHGSTATUS bit from INT.

•

ACKINT2(7:0) - a bit set masks the corresponding REGSTATUS bit from INT.

The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:

•

MASK1(7:0) - a bit set in this register masks CHGSTATUS from INT.

•

MASK2(7:0) - a bit set in this register masks REGSTATUS from INT.

•

MASK3(7:4) - a bit set in this register detects a rising edge on GPIO.

•

MASK3(7:4) - a bit cleared in this register detects a falling edge on GPIO.

•

MASK3(3:0) - a bit set in this register clears GPIO Detect signal from INT.

GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read

from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on

which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines

whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by

setting the relevant MASK3<3:0> bit; this must be done by the CPU, there is no auto-acknowledge for the GPIO

interrupts.

TPS65011 Datasheet(PDF) 38 Page - Texas Instruments

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