TPS65011 datasheet(46/52 Pages) TI

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VDCDC2 Register (Address: 0Dh—Default Value: 60h/70h)

TPS65011

SLVS501 – FEBRUARY 2004

Bit 6-Bit 5 - UVLO<1:0>: The undervoltage threshold voltage is set by UVLO1 and UVLO0 according to the

below table, with the default value in bold.

UVLO1

UVLO0

VUVLO

2.5 V

2.75 V

3.0 V

3.25 V

Bit 4 - ENABLE SUPPLY (selects between LOW POWER mode and WAIT mode):

•

0 = WAIT mode allowed, activated when LOW_PWR pin = 1 and VDCDC1 < 3 >= 1.

•

1 = The TPS65011 enters LOW POWER mode when LOW_PWR pin = 1 and VDCDC1 < 3 >= 1.

Bit 3 - ENABLE LP:

•

0 = disables the low power function of the LOW_PWR pin.

•

1 = enables the low power function of the LOW_PWR pin.

Bit 2 - MAIN DISCHARGE:

•

0 = disable the active discharge of the VMAIN converter output.

•

1 = enable the active discharge of the VMAIN converter output, when the converter is disabled (i.e., in WAIT

mode).

Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to the following table, with the

default values in bold set by the DEFMAIN pin. The default voltage can subsequently be over-written via the

serial interface after start-up.

MAIN1

MAIN0

VMAIN

2.5 V

2.75 V

3.0 V

3.3 V

VDCDC2

CORE

Bit name

LP_COREOFF

CORE2

CORE1

CORE0

CORELP1

CORELP0

VIB

DISCHARGE

Default

DEFCORE

Read/write

R/W

The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8

steps between 0.85 V and 1.8 V. The default value is governed by the DEFCORE pin; DEFCORE=0 sets an

output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.8 V.

Bit 7 - LP_COREOFF:

•

0 = VCORE converter is enabled in low power mode.

•

1 = VCORE converter is disabled in low power mode.

TPS65011 Datasheet(PDF) 46 Page - Texas Instruments

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