TSB81BA3 datasheet(26/57 Pages) TI

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TSB81BA3, TSB81BA3I

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

power-up reset

To ensure proper operation of the TSB81BA3 the RESETz terminal must be asserted low for a minimum of 2 ms

from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor

on the RESETz terminal to generate a power-on reset signal, the minimum reset time is assured if the value

of the capacitor satisfies the following equation (the value must be no smaller than approximately 0.1

µF):

Cmin = 0.0077 × T + 0.085 + external_oscillator_start-up_time

where Cmin is the minimum capacitance on the RESETz terminal in µF, T is the VDD ramp time, 10%−90%, in

ms, external_oscillator_start-up_time is the time from power applied to the external oscillator till the oscillator

outputs a valid clock in ms.

crystal oscillator selection

The TSB81BA3 is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal to

provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks required

for transmission and resynchronization of data at the S100 through S800 media data rates.

A variation of less than

±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent

PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must

be able to compensate for this difference over the maximum packet length. Larger clock variations may cause

resynchronization overflows or underflows, resulting in corrupted packet data.

For the TSB81BA3, the PCLK output may be used to measure the frequency accuracy and stability of the

internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b

LLC, the frequency of the PCLK output must be within

±100 ppm of the nominal frequency of 49.152 MHz. When

operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within

±100 ppm

of the nominal frequency of 98.304 MHz.

The following are some typical specifications for an oscillator used with the TSB81BA3 physical layer from TI in

order to achieve the required frequency accuracy and stability:

D RMS jitter of 5 picoseconds or better

D RMS phase noise jitter of 1 picosecond or less over the range 12 kHz to 20 MHz or better

D Frequency tolerance at 25_C: Total frequency variation for the complete circuit is ±100 ppm. A device with

±30 ppm or ±50 ppm frequency tolerance is recommended for adequate margin.

D Frequency stability (over temperature and age): A device with ±30 ppm or ±50 ppm frequency stability is

recommended for adequate margin.

NOTE:

The total frequency variation must be kept below

±100 ppm from nominal with some allowance for

error introduced by board and device variations. Trade-offs between frequency tolerance and

stability may be made as long as the total frequency variation is less than

±100 ppm. For example,

the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance

may be specified at 30 ppm to give a total of 80 ppm possible variation due to the oscillator alone.

Aging also contributes to the frequency variation.

It is strongly recommended that part of the verification process for the design is to measure the frequency of the

PCLK output of the PHY. This should be done with a frequency counter with an accuracy of 6 digits or better.

TSB81BA3 Datasheet(PDF) 26 Page - Texas Instruments

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