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Overvoltage Input Clamps

The MAX11158 includes an input clamping circuit that

activates when the input voltage at AIN+ is above (VDD

+ 300mV) or below -(VDD + 300mV). The clamp circuit

remains high impedance while the input signal is within

the range of Q(VDD + 100mV) and draws little to no cur-

rent. However, when the input signal exceeds this range

the clamps begin to turn on. Consequently, to obtain the

highest accuracy, ensure that the input voltage does not

exceed the range of Q(VDD + 100mV).

To make use of the input clamps, connect a resistor (RS)

between the AIN+ input and the voltage source to limit the

voltage at the analog input and to ensure the fault current

into the devices does not exceed Q20mA. Note that the

voltage at the AIN+ input pin limits to approximately 7V

during a fault condition so the following equation can be

used to calculate the value of RS:

MAX

FAULT

20mA

−

where VFAULTMAX is the maximum voltage that the

source produces during a fault condition.

Figure 1 and Figure 2 illustrate the clamp circuit volt-

age current characteristics for a source impedance

RS = 1280I. While the input voltage is within the Q(VDD

+ 300mV) range, no current flows in the input clamps.

Once the input voltage goes beyond this voltage range,

the clamps turn on and limit the voltage at the input pin.

Reference

The MAX11158 includes a precision internal reference

source as well as an internal reference buffer circuit to

drive the converter. The internal reference buffer requires

a low inductance and ESR external decoupling capacitor

of at least 10µF to be placed as close as possible to the

reference pin.

Input Amplifier

The conversion results are accurate when the ADC

acquires the input signal for an interval longer than the

input signal's worst-case settling time. The ADC input

sampling capacitor charges during the acquisition period.

During this acquisition period, the settling of the sampled

voltage is affected by the source resistance and the input

sampling capacitance. Sampling error can be estimated

by modeling the time constant of the total input capaci-

tance and the driving source impedance.

Figure 1. Input Clamp Characteristics

Figure 2. Input Clamp Characteristics (Zoom In)

MAX11158 INPUT CLAMP

CHARACTERISTICS

SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V)

-20 -10

-30

-20

-15

-10

-5

-25

-40

RS = 1280I

VDD = 5.0V

AIN+ PIN

INPUT SOURCE

MAX11158 INPUT CLAMP

CHARACTERISTICS

SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V)

-5

-15

-5

-25

-10

RS = 1280I

VDD = 5.0V

AIN+ PIN

INPUT SOURCE

MAX11158

18-Bit, 500ksps, ±5V SAR ADC with

Internal Reference in µMAX

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