MAX11167 datasheet(2/26 Pages) MAXIM

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VDD to GND.............................................................-0.3V to +6V

OVDD to GND........ -0.3V to the lower of (VDD + 0.3V) and +6V

AIN+ to GND......................................................................... ±7V

AIN-, REF,to GND..................-0.3V to the lower of (VDD + 0.3V)

and +6V

SCLK, SDI, SDO, CNVST

to GND............... -0.3V to the lower of (VDD + 0.3V) and +6V

Maximum Current into Any Pin...........................................50mA

Continuous Power Dissipation (TA = +70°C)

µMAX (derate 8.8mW/°C above +70°C)......................707mW

Operating Temperature Range...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range............................ -65°C to +150°C

Lead Temperature (soldering, 10s)..................................+300°C

Soldering Temperature (reflow).......................................+260°C

µMAX

Junction-to-Ambient Thermal Resistance (θJA)..........113°C/W

Junction-to-Case Thermal Resistance (θJC)................36°C/W

(Note 1)

(VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, TA = TMIN to TMAX, unless otherwise noted. Typical values are

at TA = +25°C.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG INPUT (Note 3)

Input Voltage Range

AIN+ to AIN-, k = 5/4.096

-VREF

x k

+VREF

x k

Absolute Input Voltage Range

AIN+ to GND

-5.1

+5.1

AIN- to GND

-0.1

+0.1

Input Leakage Current

Acquisition phase

-10

+0.001

+10

µA

Input Capacitance

Input-Clamp Protection Current

Both inputs

-20

+20

STATIC PERFORMANCE (Note 4)

Resolution

Bits

No Missing Codes

Bits

Offset Error

VOVDD ≤ 3.6V

-18

±4

+18

LSB

VOVDD > 3.6V

-32

+32

Offset Temperature Coefficient

±0.08

LSB/°C

Gain Error

VOVDD ≤ 3.6V

-24

+24

LSB

VOVDD > 3.6V

-30

+30

Gain Error Temperature Coefficient

±0.04

LSB/°C

Integral Nonlinearity

INL

VOVDD ≤ 3.6V

-6

±2.7

LSB

VOVDD > 3.6V

-9

Differential Nonlinearity

DNL

Guaranteed by design

-1.0

±0.5

LSB

Positive Full-Scale Error

VOVDD ≤ 3.6V

-22

+22

LSB

VOVDD > 3.6V

-33

+33

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to

www.maximintegrated.com/thermal-tutorial.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Thermal Characteristics

Electrical Characteristics

MAX11158

18-Bit, 500ksps, ±5V SAR ADC with

Internal Reference in µMAX

www.maximintegrated.com

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