LM2711 datasheet(17/20 Pages) NSC

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Operation (Continued)

performance of the buffers. If the capacitance presented by

the load is less than 5nF external components will be re-

quired as the load itself will not ensure stability. No external

compensation in this case will lead to oscillation of the buffer

and an increase in power consumption. A single 5nF or

greater capacitor on the output will ensure a stable buffer

with no oscillations. For applications requiring a higher slew

rate, a good choice for compensation is to add a 50

Ω (Rox)

in series with a 1nF (Cox) capacitor from the output of the

buffer to ground. This allows for driving zero to infinite ca-

pacitance loads with no oscillations, minimal overshoot, and

a higher slew rate than using a large capacitor. The high

phase margin created by the external compensation will

guarantee stability and good performance for all conditions.

For noise sensitive applications greater output capacitance

may be desired. When the power supply for the buffers (Vs+)

is connected to the output of the switching regulator, the

output ripple of the regulator will produce ripple at the output

of the buffers.

LAYOUT CONSIDERATIONS

The LM2711 uses two separate ground connections, GND

for the driver and NMOS power device of the boost regulator

and AGND for the sensitive analog control circuitry of the

boost regulator and the V

COM and Gamma buffers. The

AGND and GND pins should be tied directly together at the

package, see Figure 3 and Figure 4. The feedback, softstart,

and compensation networks should be connected directly to

a dedicated analog ground plane and this ground plane must

connect to the AGND pin, as in Figure 3. If no analog ground

plane is available then the ground connections of the feed-

back, softstart, and compensation networks must tie directly

to the AGND pin, as show in Figure 4. Connecting these

networks to the GND pin can inject noise into the system and

effect performance. For 600kHz operation the FSLCT pin

should be tied to an analog ground plane or directly to the

AGND pin. For 1.25MHz operation the FSLCT pin should be

tied to the V

IN pin.

The input bypass capacitor C

IN must be placed close to the

IC. This will reduce copper trace resistance which effects

input voltage ripple of the IC. For additional input voltage

filtering, a 100nF bypass capacitor can be placed in parallel

with C

IN, close to the VIN pin, to shunt any high frequency

noise to ground. The output capacitor, C

OUT, should also be

placed close to the IC. Any copper trace connections for the

OUT capacitor can increase the series resistance, which

directly effects output voltage ripple and efficiency. The feed-

back network, resistors R1 and R2, should be kept close to

the FB pin, and away from the inductor, to minimize copper

trace connections that can inject noise into the system.

Trace connections made to the inductor and schottky diode

should be minimized to reduce power dissipation and in-

crease overall efficiency.

20046852

FIGURE 3. Multi-Layer Layout

20046853

FIGURE 4. Single Layer Layout

LM2711 Datasheet(PDF) 17 Page - National Semiconductor (TI)

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