83058 Datasheet

©2015 Integrated Device Technology, Inc

December 15, 2015

2

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

C

PD

Power Dissipation Capacitance

(per output)

V

DDO

= 3.465V

18

pF

V

DDO

= 2.625V

20

pF

V

DDO

= 1.89V

30

pF

R

OUT

Output Impedance

V

DDO

= 3.465V

7

Ω

V

DDO

= 2.625V

7

Ω

V

DDO

= 1.89V

10

Ω

Number

Name

Type

Description

1

Q

Output

Single-ended clock output. LVCMOS/LVTTL interface levels.

2, 4, 6, 8,

9, 11,

13, 15

CLK7, CLK6, CLK5,

CLK4, CLK3, CLK2,

CLK1, CLK0

Input

Pulldown

Single-ended clock inputs. LVCMOS/LVTTL interface levels.

3

OE

Input

Pullup

Output enable. When LOW, outputs are in HIGH impedance state.

When HIGH, outputs are active. LVCMOS / LVTTL interface levels.

5

GND

Power

Power supply ground.

7, 10, 14

SEL2, SEL1, SEL0

Input

Pulldown

Clock select input. See Control Input Function Table.

LVCMOS / LVTTL interface levels.

12

V

DD

Power

Core and input supply pin.

16

V

DDO

Power

Output supply pin.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Control Inputs

Input Selected to Q

SEL2

SEL1

SEL0

0

0

0

CLK0

0

0

1

CLK1

0

1

0

CLK2

0

1

1

CLK3

1

0

0

CLK4

1

0

1

CLK5

1

1

0

CLK6

1

1

1

CLK7