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83058 Datasheet(PDF) 6 Page - Integrated Device Technology

Part # 83058
Description  8:1, Single-Ended Multiplexer
PDF  14 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

83058 Datasheet(HTML) 6 Page - Integrated Device Technology

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83058 Datasheet
©2015 Integrated Device Technology, Inc
December 15, 2015
6
TABLE 5D. AC CHARACTERISTICS, V
DD
= V
DDO
= 2.5V ± 5%, TA = -40°C TO 85°C
TABLE 5E. AC CHARACTERISTICS, V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ± -5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
f
MAX
Output Frequency
250
MHz
tp
LH
Propagation Delay, Low to High; NOTE 1
1.9
2.7
3.5
ns
tp
HL
Propagation Delay, High to Low; NOTE 1
2.5
2.9
3.4
ns
tsk(i)
Input Skew; NOTE 2
60
175
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.21
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
300
ps
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
100
500
ps
odc
Output Duty Cycle
40
60
%
MUX
ISOL
MUX Isolation
@ 100MHz
45
dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
f
MAX
Output Frequency
250
MHz
tp
LH
Propagation Delay, Low to High; NOTE 1
2.2
2.9
4.0
ns
tp
HL
Propagation Delay, High to Low; NOTE 1
2.7
3.3
4.0
ns
tsk(i)
Input Skew; NOTE 2
50
150
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.17
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
325
ps
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
100
700
ps
odc
Output Duty Cycle
40
60
%
MUX
ISOL
MUX Isolation
@ 100MHz
45
dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.



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