5-80

TABLE 2. FUNCTION PIN DEFINITION

PIN

SYMBOL

DESCRIPTION

Positive Power Supply

2

N/C

No Connection

3

GND

4

RRD

A high level on RECEIVER REGISTER DISABLE forces the receiver holding register ouputs RBR1-RBR8 to

a high impedance state.

5

RBR8

The contents of the RECEIVER BUFFER REGISTER appear on these three-state outputs. Word formats less

than 8 characters are right justified to RBR1.

6

RBR7

See Pin 5 - RBR8

7

RBR6

8

RBR5

9

RBR4

10

RBR3

11

RBR2

12

RBR1

13

PE

A high level on PARITY ERROR indicates that the received parity does not match parity programmed by control

bits. The output is active until parity matches on a succeeding character. When parity is inhibited, this output

is low.

14

FE

A high level on FRAMING ERROR indicates the first stop bit was invalid. FE will stay active until the next valid

character’s stop bit is received.

15

OE

A high level on OVERRUN ERROR indicates the data received flag was not cleared before the last character

was transferred to the receiver buffer register. The Error is reset at the next character’s stop bit if DRR has been

performed (i.e., DRR; active low).

16

SFD

A high level on STATUS FLAGS DISABLE forces the outputs PE, FE, OE, DR, TBRE to a high impedance

state.

17

RRC

The RECEIVER REGISTER CLOCK is 16X the receiver data rate.

18

DRR

A low level on DATA RECEIVED RESET clears the data received output (DR), to a low level.

19

DR

A high level on DATA RECEIVED indicates a character has been received and transferred to the receiver buffer

register.

20

RRl

Serial data on RECEIVER REGISTER INPUT is clocked into the receiver register.

21

MR

A high level on MASTER RESET (MR) clears PE, FE, OE and DR, and sets TRE, TBRE, and TRO. TRE is

actually set on the first rising edge of TRC after MR goes high. MR should be strobed after power-up.

22

TBRE

A high level on TRANSMITTER BUFFER REGISTER EMPTY indicates the transmitter buffer register has

transferred its data to the transmitter register and is ready for new data.

23

TBRL

A low level on TRANSMITTER BUFFER REGISTER LOAD transfers data from inputs TBR1-TBR8 into the

transmitter buffer register. A low to high transition on TBRL requests data transfer to the transmitter register. If

the transmitter register is busy, transfer is automatically delayed so that the two characters are transmitted end

to end.

24

TRE

A high level on TRANSMITTER REGISTER EMPTY indicates completed transmission of a character including

stop bits.

CDP6402, CDP6402C