IR35201 datasheet(36/60 Pages) IRF

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8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller

IR35201

February 8, 2015 | V1.6

The controller does not shutdown the circuitry for

lowest power consumption.

PS4 wake up can be set to wake on any SVID clock

or alternatively on any SVID Set_VID or SetPS0/1/2/3

command.

PS4 REGISTER SUPPORT

IR35201 controller supports SVID register “PS4 Exit

Latency” (2B). This register holds the encoded value for PS4

exit latency calculated as

( )=16∗2

Where x =bits[3:0], y = bits[7:4]

FAULTS & PROTECTION

The comprehensive fault coverage of the IR35201

protects the VR against a variety of fault conditions.

Faults can be configured and monitored through the

IR PowIRCenter GUI. There are two types of fault

monitoring registers. In addition to real-time fault

registers, there are “sticky” fault registers that can only

be cleared with an I2C command or 3.3V power cycle.

These will indicate if any fault has occurred since the

last power cycle, even if the fault has cleared itself

and the VR has resumed normal operation.Table 27

lists the available faults.

TABLE 27: STICKY & NON-STICKY FAULTS

Faults

Sticky

OTP, OCP, OVP, UVP,

VIN UVLO, 3.3V UVLO,

phase-fault, slow-OCP

Non-Sticky

Output Over-voltage Protection (OVP)

If the output voltage exceeds a user-programmable

threshold (Table 32) above the VID set-point, the

IR35201 detects an output over-voltage fault and

latches ON the low-side MOSFETS to limit the output

voltage rise.

TABLE 28: OVP ACTION

OVP Action

Low-side MOSFET latched on

Low-side MOSFET on until

Output<0.248V

Per Table 28 above, the low-side MOSFETs may be

configured to either latch ON indefinitely (Figure 40) or

stay ON until the output voltage falls below the

release threshold (Figure 41), in case of an over-

voltage condition. This release mode reduces the

undershoot of the output voltage during recovery from

an OVP condition. If the output voltage rises above

the OVP threshold during recovery, the low side

MOSFET’s will again be turned on until Vout drops

below the release threshold level. Note that OVP is

disabled during a DVID-down event to prevent false

triggering.

During soft-start, OVP is triggered at a user-selectable

level from one of the thresholds listed in Table 29

below.

TABLE 29: OVP THRESHOLDS DURING START-UP

Value

Threshold

2.5V

1.2V

1.275V

1.35V

The IR35201 also provides the option to allow OVP to

remain active when the device is disabled, in order to

prevent system leakage from causing over-voltage on

the output (Table 30).

Note: OVP functionality is only available when both

the controller and drivers or power stages have Vcc

power.

TABLE 30: OVP OPTIONS

OVP_when-disabled setting

When active

IC disabled & IC enabled

Off

IC enabled

Figure 40: OVP - MOSFET latched on

IR35201 Datasheet(PDF) 36 Page - International Rectifier

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