FLASH

AS8F128K32

AS8F128K32

Rev. 2.8 01/10

Micross Components reserves the right to change products or specifications without notice.

3

DEVICE BUS OPERATIONS

NOTE: All device/algorithm descriptions contained in this

data sheet reference each individual die.

This section describes the requirements and use of the

device bus operations, which are initiated through the inter-

nal command register. The command register itself does not

occupy any addressable memory location. The register is

composed of latches that store the commands, along with the

address and data information needed to execute the command.

The contents of the register serve as inputs to the internal state

machine. The state machine outputs dictate the function of

the device. The appropriate device bus operations table lists

the inputs and control levels required, and the resulting output.

The following subsections describe each of these operations in

further detail.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the CEx\ and OE\ pins to V

IL

. CEx\ is the power control and

selects the device. OE\ is the output control and gates array

data to the output pins. WEx\ should remain at V

IH

.

The internal state machine is set for reading array data

upon device power-up. This ensures that no spurious altera-

tion of the memory content occurs during the power transition.

No command is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid addresses

on the device address inputs produce valid data on the device

data outputs. The device remains enabled for read access until

the command register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifications and

to the Read Operations Timings diagram for the timing wave-

forms. I

CC1

in the DC Characteristics table represents the active

current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing sectors of

memory), the system must drive WEx\ and CEx\ to V

IL

, and

OE\ to V

IH

.

An erase operation can erase one sector, multiple sectors, or

the entire device. The Sector Address Tables indicate the address

space that each sector occupies. A “sector address” consists of

the address bits required to uniquely select a

sector. See the

“Command Definitions” section for details on erasing a sector

or the entire chip.

After the system writes the autoselect command se-

quence,

the device enters the autoselect mode. The system can then read

autoselect codes from the internal register (which is

separate

from the memory array) on I/O31–I/O0. Standard read cycle

timings apply in this mode. Refer to the “Autoselect Mode”

and “Autoselect Command Sequence” sections for more

information. I

CC2

in the DC Characteristics table represents

the active current specification for the write mode. The “AC

Characteristics” section contains timing specification tables

OPERATION

CEx\

OE\

WEx\

ADRESSES

(A16:A0)

I/O0 - I/O31

Read

L

L

H

Write

L

H

L

Standby

X

X

X

High-Z

Output Disable

L

H

H

X

High-Z

Hardware Reset

X

X

X

X

High-Z

Temporary Sector Unprotect

X

X

X

LEGEND:

L = Logic Low = V

IL

, H = Logic High = V

IH

, V

ID

= 12.0 ± 0.5 V, X = Don’t Care, A

IN

= Addresses In, D

IN

= Data In, D

OUT

= Data Out

NOTES:

1. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section.