SST38VF6402 datasheet(12/64 Pages) MICROCHIP

12 / 64 page

DS-20005015B

08/15

64 Mbit (x16) Advanced Multi-Purpose Flash Plus

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Not Recommended for New Designs

To resume a suspended Sector-Erase or Block-Erase operation, the system must issue the Erase-

Resume command. The operation is executed by issuing one byte command sequence with Erase-

Resume command (30H) at any address in the last Byte sequence.

When an erase operation is suspended, or re-suspended, after resume the cumulative time needed for

the erase operation to complete is greater than the erase time of a non-suspended erase operation. If

the hold time from Erase-Resume to the next Erase- Suspend operation is less than 200µs, the accu-

mulative erase time can become very long Therefore, after issuing an Erase-Resume command, the

system must wait at least 200µs before issuing another Erase-Suspend command. The Erase-Resume

command will be ignored until any program operations initiated during Erase-Suspend are complete.

Bypass mode can be entered while in Erase-Suspend, but only Bypass Word-Program is available for

those sectors or blocks that are not suspended. Bypass Sector-Erase, Bypass Block-Erase, and

Bypass Chip-Erase, Erase-Suspend, and Erase-Resume are not available. In order to resume an

Erase operation, the Bypass mode must be exited before issuing Erase-Resume. For more information

about Bypass mode, see “Bypass Mode” on page 17.

Chip-Erase Operation

The SST38VF6401/6402/6403/6404 devices provide a Chip-Erase operation, which erases the entire

memory array to the ‘1’ state. This operation is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase

command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising

edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads

are Toggle Bit, Data# Polling, or RY/BY#. See Table 11 for the command sequence, Figure 13 for tim-

ing diagram, and Figure 29 for the flowchart. Any commands issued during the Chip-Erase operation

are ignored. If WP# is low, or any VPBs or NVPBs are in the protect state, any attempt to execute a

Chip-Erase operation is ignored. During the command sequence, WP# should be statically held high

or low.

Write Operation Status Detection

To optimize the system Write cycle time, the SST38VF6401/6402/6403/6404 provide two software

means to detect the completion of a Write (Program or Erase) cycle The software detection includes

two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled

after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system. Therefore, Data# Poll-

ing or Toggle Bit maybe be read concurrent with the completion of the write cycle. If this occurs, the

system may possibly get an incorrect result from the status detection process. For example, valid data

may appear to conflict with either DQ7 or DQ6. To prevent false results, upon detection of failures, the

software routine should loop to read the accessed location an additional two times. If both reads are

valid, then the device has completed the Write cycle, otherwise the failure is valid.

For the Write-Buffer Programming feature, DQ1 informs the user if either the Write-to-Buffer or Pro-

gram Buffer-to-Flash operation aborts. If either operation aborts, then DQ1 = 1. DQ1 must be cleared to

'0' by issuing the Write-to-Buffer Abort Reset command.

The SST38VF6401/6402/6403/6404 also provide a RY/BY# signal. This signal indicates the status of a

Program or Erase operation.

SST38VF6402 Datasheet(PDF) 12 Page - Microchip Technology

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